Cortex-A8 R2P2.pdf - ARM Information Center

Embedded Trace Macrocell14.10 Interaction with the Performance Monitoring UnitThe processor includes a Performance Monitoring Unit (PMU) that enables events,such as cache misses and instructions executed, to be counted over a period of time. Thissection describes how the PMU and ETM are used together.14.10.1 Use of PMU events by the ETMThe PMU events are all available for use by the ETM using the extended external inputfacility. Each event is mapped to one or two extended external inputs. For moreinformation on PMU events, see c9, Event Selection Register on page 3-111.A PMU event uses two extended external inputs where two such events can occur in acycle. Both extended external inputs are active in cycle when two events occur. TheETM Architecture Specification describes how to use extended external input selectorsto make these events available to the rest of the ETM triggering and filtering logic.Table 14-17 shows the mapping of the PMU event numbers to the ETM extendedexternal input event numbers.Table 14-17 PMU event number mappingsPMU event number First ETM event number Second ETM event number0x0 - -0x1 0x1 -0x2 0x2 -0x3 0x3 -0x4 0x5 -0x5 0x6 -0x6 0x7 -0x7 0x8 -0x8 0x9 0xa0x9 0xb -0xa 0xc -0xb 0xd -0xc 0xe -14-32 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E