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Debug12.2.4 Programming the debug unitEmbedded Trace Macrocell for information on ETM. See Chapter 3System Control Coprocessor for information on performance monitorregisters.SPNIDEN and SUNIDEN control noninvasive debug permissions.The processor debug unit is programmed using the APB interface. See Table 12-3 onpage 12-9 for a complete list of memory-mapped debug registers accessible using theAPB interface. Some features of the debug unit that you can access using thememory-mapped registers are:• instruction address comparators for triggering breakpoints, see Breakpoint ValueRegisters on page 12-37 and Breakpoint Control Registers on page 12-38• data address comparators for triggering watchpoints, see Watchpoint ValueRegisters on page 12-42 and Watchpoint Control Registers on page 12-43• a bidirectional Debug Communication Channel (DCC), see Debugcommunications channel on page 12-95• all other state information associated with the debug unit.12-6 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E
Debug12.3 Debug register interfaceYou can access the debug register map using the APB interface. This is the only way toget full access to the processor debug capability. ARM recommends that if your systemrequires the processor to access its own debug registers, you choose a systeminterconnect structure that enables the processor to access the APB interface byexecuting load and stores to a certain area of physical memory.12.3.1 Coprocessor registersAlthough most of the debug registers are accessible through the memory-mappedinterface, there are several registers that you can access through a coprocessor interface.This is important for boot-strap access to the ARM register file. It enables softwarerunning on the processor to identify the debug architecture version implemented by thedevice.12.3.2 CP14 access permissionsBy default, you can access all CP14 debug registers from a nonprivileged mode.However, you can program the processor to disable user-mode access to all coprocessorregisters using bit [12] of the DSCR, see CP14 c1, Debug Status and Control Registeron page 12-21 for more information. CP14 debug registers accesses are alwayspermitted while the processor is in debug state regardless of the processor mode.Table 12-1 shows access to the CP14 debug registers.Table 12-1 Access to CP14 debug registersDebug state Processor mode DSCR[12] CP14 debug accessYesX aX aPermittedNo User b0 PermittedNo User b1 UndefinedNo Privileged X a Permitteda. X indicates a Don’t care condition. The outcome does not depend on thiscondition.12.3.3 Coprocessor registers summaryTable 12-2 on page 12-8 shows the valid CP14 debug instructions for accessing thedebug registers. All CP14 debug instructions not listed are Undefined.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 12-7
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Cortex -A8Revision: r2p2Technical R
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Product StatusThe information in th
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ContentsCortex-A8 Technical Referen
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Contents7.8 Parity detection ......
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ContentsA.2 ATB interface .........
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List of TablesCortex-A8 Technical R
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List of TablesTable 3-103 Results o
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List of TablesTable 12-1 Access to
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List of TablesTable 15-3 CTI regist
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List of Tablesxx Copyright © 2006-
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List of FiguresFigure 3-10 Memory M
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List of FiguresFigure 10-13 Retenti
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List of FiguresFigure 15-16 CTI Cha
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PrefaceAbout this manualThis is the
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PrefaceChapter 16 Instruction Cycle
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PrefacePrefix CPrefix HPrefix nPref
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PrefaceFeedbackARM welcomes feedbac
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Introduction1.1 About the processor
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Introduction1.3 Components of the p
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Introduction1.3.4 Load/storeThe loa
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Introduction1.4 External interfaces
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Introduction1.6 Power managementThe
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Introduction1.8 Product revisionsTh
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Introduction1-14 Copyright © 2006-
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Programmer’s Model• Hardware co
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Programmer’s Model2.2 Thumb-2 ins
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Programmer’s Model2.3 ThumbEE ins
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Programmer’s ModelThumbEE Handler
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Programmer’s Model2.4 Jazelle Ext
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Programmer’s Model— the registe
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Programmer’s ModelNonsecureSecure
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Programmer’s Model2.7 VFPv3 archi
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Programmer’s Model2.9 Data typesT
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Programmer’s ModelBitHigher addre
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Programmer’s Model2.12 Operating
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Programmer’s ModelIn privileged m
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Programmer’s Model16 generalpurpo
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Programmer’s ModelIn ARM state, y
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Programmer’s Model2.14.5 The GE[3
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Programmer’s ModelT bitThe T bit
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Programmer’s ModelOnly secure pri
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Programmer’s Model2.15.2 Leaving
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Programmer’s ModelAn internal or
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Programmer’s ModelImprecise data
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Programmer’s ModelNoteIf the Embe
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Programmer’s Model2.16 Software c
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Programmer’s Model2.17.2 Security
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Programmer’s Model2.18 Control co
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System Control Coprocessor3.1 About
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System Control CoprocessorTable 3-1
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System Control CoprocessorSecurity
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System Control Coprocessor3.2.20 c0
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System Control CoprocessorThe Auxil
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System Control CoprocessorVA to PA
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System Control CoprocessorInvalidat
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System Control CoprocessorThe PMNC
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System Control Coprocessorb. The EN
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System Control Coprocessor• acces
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System Control CoprocessorYou can c
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System Control CoprocessorIf the op
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System Control CoprocessorTo access
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System Control CoprocessorTo access
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System Control CoprocessorLDR R1, =
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System Control CoprocessorL1 Data 0
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System Control CoprocessorInstructi
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System Control CoprocessorParity/EC
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System Control CoprocessorL2 parity
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System Control CoprocessorThe L2 da
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Chapter 4Unaligned Data and Mixed-e
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Unaligned Data and Mixed-endian Dat
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Unaligned Data and Mixed-endian Dat
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Chapter 5Program Flow PredictionThi
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Program Flow Prediction5.2 Predicte
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Program Flow Prediction5.2.1 Return
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Program Flow Prediction5.4 Guidelin
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Program Flow Prediction5.6 Operatin
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Chapter 6Memory Management UnitThis
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Memory Management Unit6.2 Memory ac
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Memory Management Unit6.4 MMU inter
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Memory Management Unit6.6 TLB lockd
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Chapter 7Level 1 Memory SystemThis
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Level 1 Memory System7.2 Cache orga
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Level 1 Memory System7.3 Memory att
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Level 1 Memory SystemTable 7-1 Memo
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Level 1 Memory System7.5 Data cache
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Level 1 Memory SystemAn exception t
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Level 1 Memory System7.8 Parity det
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Chapter 8Level 2 Memory SystemThis
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Level 2 Memory System8.2 Cache orga
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Level 2 Memory System8.3 Enabling a
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Level 2 Memory SystemControl Regist
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Chapter 9External Memory InterfaceT
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External Memory Interfaceto the wri
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External Memory InterfaceTable 9-2
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External Memory Interface9.3 AXI in
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External Memory InterfaceBWBCNoTTSS
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Chapter 10Clock, Reset, and Power C
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Clock, Reset, and Power Controlfami
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Clock, Reset, and Power Control10.2
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Clock, Reset, and Power Control•
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Clock, Reset, and Power Control2. F
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Clock, Reset, and Power ControlNote
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Clock, Reset, and Power ControlAfte
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Clock, Reset, and Power Control—
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Clock, Reset, and Power ControlPowe
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DebugBits Field FunctionTable 12-35
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Debug12.9 Cache debugThere are seve
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Debug12.10 External debug interface
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DebugDBGROMADDRThe DBGROMADDR signa
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Debug4. Issue an Instruction Synchr
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Debug12.11.1 Debug communications c
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Chapter 13NEON and VFP Programmer
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NEON and VFP Programmer’s Modelre
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Chapter 14Embedded Trace MacrocellT
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Embedded Trace Macrocell14.1.2 The
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Chapter 15Cross Trigger InterfaceTh
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Cross Trigger Interface• An input
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Chapter 16Instruction Cycle TimingT
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Instruction Cycle Timing16.2 Instru
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Instruction Cycle TimingTable 16-4
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Instruction Cycle Timing16.2.7 Stat
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Instruction Cycle TimingThe number
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Instruction Cycle Timing16.3 Dual-i
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Instruction Cycle TimingReplayevent
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Instruction Cycle TimingPredicting
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AC CharacteristicsThe timing parame
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AC CharacteristicsTable 17-2 Timing
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AC Characteristics17.5 L1 and L2 MB
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AC Characteristics17.7 DFT interfac
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AC Characteristicsb. Figure 10-6 on
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Appendix ASignal DescriptionsThis a
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Signal DescriptionsA.2 ATB interfac
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Signal DescriptionsTable A-3 MBIST
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Signal DescriptionsA.4 Preload engi
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Signal DescriptionsTable A-7 Miscel
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Signal DescriptionsA.8 Miscellaneou
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Appendix BInstruction MnemonicsThis
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Instruction MnemonicsTable B-1 Adva
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Instruction MnemonicsB.2 VFP data-p
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GlossaryThis glossary describes som
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GlossaryApplication Specific Integr
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GlossaryRead ID capabilityThe maxim
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GlossaryByte-invariantIn a byte-inv
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GlossaryCAM includes comparison log
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GlossaryDouble-precision valueConsi
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Glossary• arithmetic operation re
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GlossaryInvalidateJazelle architect
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GlossaryPAPenaltyPower-on resetPref
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GlossarySetSet-associative cacheSee
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GlossaryTrapTrigger instructionAn e
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GlossaryWrite-back (WB)Write buffer
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