Cortex-A8 R2P2.pdf - ARM Information Center

Contents2.8 Processor operating states ....................................................................... 2-172.9 Data types ................................................................................................ 2-182.10 Memory formats ........................................................................................ 2-192.11 Addresses in a processor system ............................................................. 2-212.12 Operating modes ...................................................................................... 2-222.13 Registers .................................................................................................. 2-232.14 The program status registers .................................................................... 2-272.15 Exceptions ................................................................................................ 2-352.16 Software consideration for Security Extensions ....................................... 2-442.17 Hardware consideration for Security Extensions ...................................... 2-452.18 Control coprocessor ................................................................................. 2-48Chapter 3Chapter 4Chapter 5Chapter 6Chapter 7System Control Coprocessor3.1 About the system control coprocessor ....................................................... 3-23.2 System control coprocessor registers ........................................................ 3-9Unaligned Data and Mixed-endian Data Support4.1 About unaligned and mixed-endian data .................................................... 4-24.2 Unaligned data access support .................................................................. 4-34.3 Mixed-endian access support ..................................................................... 4-5Program Flow Prediction5.1 About program flow prediction .................................................................... 5-25.2 Predicted instructions ................................................................................. 5-35.3 Nonpredicted instructions ........................................................................... 5-65.4 Guidelines for optimal performance ............................................................ 5-75.5 Enabling program flow prediction ............................................................... 5-85.6 Operating system and predictor context ..................................................... 5-9Memory Management Unit6.1 About the MMU ........................................................................................... 6-26.2 Memory access sequence .......................................................................... 6-36.3 16MB supersection support ........................................................................ 6-46.4 MMU interaction with memory system ........................................................ 6-56.5 External aborts ........................................................................................... 6-66.6 TLB lockdown ............................................................................................. 6-76.7 MMU software-accessible registers ............................................................ 6-8Level 1 Memory System7.1 About the L1 memory system ..................................................................... 7-27.2 Cache organization ..................................................................................... 7-37.3 Memory attributes ....................................................................................... 7-57.4 Cache debug .............................................................................................. 7-87.5 Data cache features ................................................................................... 7-97.6 Instruction cache features ........................................................................ 7-107.7 Hardware support for virtual aliasing conditions ....................................... 7-12vi Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E