Cortex-A8 R2P2.pdf - ARM Information Center

GlossaryBig-endianByte ordering scheme in which bytes of decreasing significance in a data word arestored at increasing addresses in memory.See also Little-endian and Endianness.Big-endian memoryMemory in which:• a byte or halfword at a word-aligned address is the most significant byte orhalfword within the word at that address• a byte at a halfword-aligned address is the most significant byte within thehalfword at that address.See also Little-endian memory.Block addressAn address that comprises a tag, an index, and a word field. The tag bits identify the waythat contains the matching cache entry for a cache hit. The index bits identify the setbeing addressed. The word field contains the word address that can be used to identifyspecific words, halfwords, or bytes within the cache entry.See also Cache terminology diagram on the last page of this glossary.Branch predictionBreakpointThe process of predicting if branches are to be taken or not in pipelined processors.Successfully predicting if branches are to be taken enables the processor to prefetch theinstructions following a branch before the branch is fully resolved. Branch predictioncan be done in software or by using custom hardware. Branch prediction techniques arecategorized as static, in which the prediction decision is decided before run time, anddynamic, in which the prediction decision can change during program execution.A breakpoint is a mechanism provided by debuggers to identify an instruction at whichprogram execution is to be halted. Breakpoints are inserted by the programmer to enableinspection of register contents, memory locations, variable values at fixed points in theprogram execution to test that the program is operating correctly. Breakpoints areremoved after the program is successfully tested.See also Watchpoint.BurstA group of transfers to consecutive addresses. Because the addresses are consecutive,there is no requirement to supply an address for any of the transfers after the first one.This increases the speed at which the group of transfers can occur. Bursts over AMBAare controlled using signals to indicate the length of the burst and how the addresses areincremented.See also Beat.ByteAn 8-bit data item.Glossary-6 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E