Cortex-A8 R2P2.pdf - ARM Information Center

System Control Coprocessorb. The EN bit in c9, User Enable Register enables User mode access of the Performance Monitor Registers.To access the PMCNT Registers, read or write CP15 with:MRC p15, 0, , c9, c13, 2; Read PMCNT0-PMCNT3 RegistersMCR p15, 0, , c9, c13, 2; Write PMCNT0-PMCNT3 RegistersTable 3-99 shows what signal settings are required and the Secure or Nonsecure stateand mode that you can enable the counters.Table 3-99 Signal settings for the Performance Monitor Count RegistersDBGEN ||NIDENSPIDEN ||SPNIDENSUNIDENSecurestateUsermodePMNC[5]Performancecounters enabledCCNTenabled0 - - - - b0 No Yes0 - - - - b1 No No1 - - No - - Yes Yes1 - - Yes - - Yes Yes1 0 - Yes No b0 No Yes1 0 - Yes No b1 No No1 0 0 Yes Yes b0 No Yes1 0 0 Yes Yes b1 No No1 0 1 Yes Yes X Yes Yes3.2.51 c9, User Enable RegisterThe purpose of the USER ENable (USEREN) Register is to enable User mode to haveaccess to the Performance Monitor Registers.NoteUSEREN Register does not provide access to the registers that control interruptgeneration.The USEREN Register is:• a read/write register common to Secure and Nonsecure states• writable only in privileged mode and readable in any processor mode.Figure 3-45 on page 3-118 shows the bit arrangement of the USEREN Register.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 3-117