Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorTable 3-3 Summary of CP15 registers and operations (continued)CRn Op1 CRm Op2Register oroperationSecurity state Reset value PageNSS1-7 c0-c15 0-7 Undefined - - - -c9 0 c0-c11 0-7 Undefined - - - -c12 0 PerformanceMonitor ControlR/W, X R/W, X 0x41002000 page 3-1011 Count Enable Set R/W, X R/W, X 0x00000000 page 3-1032 Count Enable Clear R/W, X R/W, X 0x00000000 page 3-1043 Overflow FlagStatusR/W, X R/W, X 0x00000000 page 3-1064 Software Increment R/W, X R/W, X 0x00000000 page 3-1075 PerformanceCounter SelectionR/W, X R/W, X Unpredictable page 3-1096-7 Undefined - - - -c13 0 Cycle Count R/W, X R/W, X 0x00000000 page 3-1101 Event Selection R/W, X R/W, X Unpredictable page 3-1112 PerformanceMonitor CountR/W, X R/W, X 0x00000000 page 3-1163-7 Undefined - - - -c14 0 User Enable R/W R/W 0x00000000 page 3-1171 Interrupt EnableSet2 Interrupt EnableClearR/W R/W 0x00000000 page 3-118R/W R/W 0x00000000 page 3-1203-7 Undefined - - - -c15 0-7 Undefined - - - -1 c0 0 L2 CacheLockdownR/W R/W 0x00000000 page 3-121ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 3-17