Cortex-A8 R2P2.pdf - ARM Information Center

DebugDBGNOPWRDWNThe processor asserts DBGNOPWRDWN when bit [0] of the Device Power Down andReset Control Register is 1. The processor power controller works in emulate modewhen this signal is HIGH.DBGPWRDWNREQYou must set the DBGPWRDWNREQ signal HIGH before removing power from thecore domain. Bit [0] of the Device Power Down and Reset Status Register reflects thevalue of this DBGPWRDWNREQ signal.NoteDBGPWRDWNREQ must be tied LOW if the particular implementation does notsupport separate core and debug power domains.DBGPWRDWNACKThis signal indicates to the system that it is safe to bring the core voltage down.Figure 12-29 shows the relationship of the DBGPWRDWNREQ andDBGPWRDWNACK signals with the core domain power-down and power-upsequences.DBGPWRDWNREQDBGPWRDWNACKVdd (core)nPORESETFigure 12-29 Timing of core power-down and power-up sequencesDBGOSLOCKINITWhen the DBGOSLOCKINIT signal is asserted on PRESETn reset, the OS lock isset. Otherwise, the OS lock is clear on PRESETn reset. ARM recommends that thissignal is tied LOW.12-90 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E