Cortex-A8 R2P2.pdf - ARM Information Center

Clock, Reset, and Power ControlThe ETM Control Register enables the ETM. See the Embedded Trace MacrocellArchitecture Specification for more information. The global enable bit in the CTIControl Register enables the ETM clocks, excluding the ATB clock, ATCLK, whichcan only be gated external to the processor. See CTI Control Register, CTICONTROLon page 15-13.DFF gatingThe finest level of dynamic power control is at the Delay Flip-Flop (DFF) level. This isimplicit to the design and requires no external support.10.3.2 Static or leakage power managementThe processor can accommodate many different levels of static, or leakage powermanagement. All of these techniques are specific to a given implementation of theprocessor. Some possibilities that the processor can accommodate are:• full retention• power domains or islands such as integer core, ETM and debug, L2 RAM, andNEON• usage of multi-Vt such as high-Vt, standard-Vt, or low-Vt.NoteThis technical reference manual does not document retention or the usage of multi-Vt.However, this manual describes the power domains, or islands that are supported andthe methods that are required to manage those domains in a manner that has beenvalidated within the processor.To completely eliminate leakage power consumption in the processor, you must removethe power supplied to the processor. Before powering down, all architectural state mustbe saved to memory and the L1 data cache or L2 unified cache must be cleaned to thepoint of coherency. When powering up the processor, you must apply a complete resetsequence with software that restores the architectural state. The sequence takessignificant time and energy to perform a full power-down of the processor.To improve the response time of a power-down sequence, the processor supports severalkey features to minimize the response time and to reduce the leakage powerconsumption:• The processor enables the debug, ETM, and NEON units to be powered downwhile the rest of the processor is active.10-14 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E