Configuration Handbook - Kamami.pl

Configuring Stratix II & Stratix II GX Devices128-bit security key is stored in the Stratix II or Stratix II GX device. Inorder to successfully configure a Stratix II or Stratix II GX device that hasthe design security feature enabled, it must be configured with aconfiguration file that was encrypted using the same 128-bit security key.The security key can be stored in non-volatile memory inside the Stratix IIor Stratix II GX device. This non-volatile memory does not require anyexternal devices, such as a battery back-up, for storage.1 When using a serial configuration scheme such as passive serial(PS) or active serial (AS), configuration time is the same whetheror not the design security feature is enabled. If the fast passiveparallel (FPP) scheme is used with the design security ordecompression feature, a 4× DCLK is required. This results in aslower configuration time when compared to the configurationtime of an FPGA that has neither the design security, nordecompression feature enabled. For more information aboutthis feature, contact Altera Applications group.Remote System UpgradeStratix II and Stratix II GX devices feature remote and local update. Formore information about this feature, refer to the chapter Remote SystemUpgrades with Stratix II & Stratix II GX Devices in volume 2 of the Stratix IIDevice Handbook or the Stratix II GX Device Handbook.Power-On Reset CircuitThe POR circuit keeps the entire system in reset until the power supplyvoltage levels have stabilized on power-up. Upon power-up, the devicedoes not release nSTATUS until V CCINT , V CCPD , and V CCIO of banks 3, 4, 7,and 8 are above the device’s POR trip point. On power down, V CCINT ismonitored for brown-out conditions.The passive serial (PS) mode (MSEL[3,2,1,0] = 0010) and the Fastpassive parallel (FPP) mode (MSEL[3,2,1,0] = 0000) always setbank 3 to use the lower POR trip point consistent with 1.8- and 1.5-Vsignaling, regardless of the VCCSEL setting. For all other configurationmodes, VCCSEL selects the POR trip-point level. Refer to the section“VCCSEL Pin” on page 7–10 for more details.In Stratix II devices, a pin-selectable option PORSEL is provided thatallows you to select between a typical POR time setting of 12 ms or100 ms. In both cases, you can extend the POR time by using an externalcomponent to assert the nSTATUS pin low.Altera Corporation 7–9May 2007 Stratix II Device Handbook, Volume 2