Configuration Handbook - Kamami.pl

Functional Descriptioncompression ratios from a suite of Stratix designs. These numbers serveas a guideline (not a specification) to help you allocate sufficientconfiguration memory to store compressed bitstreams.Table 2–4. Stratix Compression Ratios Note (1)MinimumAverageLogic Utilization 98% 64%Compression Ratio 1.9 2.3% Size Reduction 47% 57%Note to Table 2–4:(1) These numbers are preliminary. They are intended to serve as a guideline, not aspecification.Programmable Configuration ClockThe configuration clock (DCLK) speed is user programmable. One of twoclock sources can be used to synthesize the configuration clock; aprogrammable oscillator or an external clock input pin (EXCLK). Theconfiguration clock frequency can be further synthesized using the clockdivider circuitry. This clock can be divided by the N counter to generateyour DCLK output. The N divider supports all integer dividers between1 and 16, as well as a 1.5 divider and a 2.5 divider. The duty cycle for allclock divisions other than non-integer divisions is 50% (for the nonintegerdividers, the duty cycle will not be 50%). See Figure 2–5 for a blockdiagram of the clock divider unit.Figure 2–5. Clock Divider UnitConfiguration DeviceClock Divider UnitExternal Clock(Up to 100 MHz)10 MHz33 MHz50 MHz66 MHzDivideby NDCLKInternal Oscillator2–18 Altera CorporationConfiguration Handbook, Volume 2 May 2007