Configuration Handbook - Kamami.pl

Fast Passive Parallel ConfigurationYou can use a single configuration chain to configure Stratix III deviceswith other Altera devices that support FPP configuration, such as Stratixdevices. To ensure that all devices in the chain complete configuration atthe same time, or that an error flagged by one device initiatesreconfiguration in all devices, tie all of the device CONF_DONE andnSTATUS pins together.fFor more information on configuring multiple Altera devices in the sameconfiguration chain, refer to Configuring Mixed Altera Device Chains in theConfiguration Handbook.FPP Configuration TimingFigure 11–6 shows the timing waveform for FPP configuration whenusing a MAX II device as an external host. This waveform shows thetiming when the decompression and the design security feature are notenabled.Figure 11–6. FPP Configuration Timing Waveform Notes (1), (2)t CFGt CF2ST1nCONFIGt CF2CKt STATUSnSTATUS (3)t CF2ST0t CLKCONF_DONE (4)t CF2CDDCLK(5)DATA[7..0]t CH t CLt DHt ST2CKHigh-ZByte 0 Byte 1 Byte 2 Byte 3 Byte n(5)User Modet DSUUser I/OUser ModeINIT_DONEt CD2UMNotes to Figure 11–6:(1) You should use this timing waveform when the decompression and design security features are not used.(2) The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS, andCONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.(3) Upon power-up, the Stratix III device holds nSTATUS low for the time of the POR delay.(4) Upon power-up, before and during configuration, CONF_DONE is low.(5) You should not leave DCLK floating after configuration. You should drive it high or low, whichever is moreconvenient.(6) DATA[7..0] are available as user I/O pins after configuration. The state of these pins depends on the dual-purposepin settings.11–18 Altera CorporationStratix III Device Handbook, Volume 1 May 2007