Configuration Handbook - Kamami.pl

Concurrent ConfigurationFPP configuration mode uses the eight DATA [7..0] lines from theenhanced configuration device, which can be used to configure Stratix ®series, and APEX II devices. To decrease configuration time, FPPconfiguration provides eight bits of configuration data per clock cycle tothe target device.ffFor more information on configuration schemes, refer to the EnhancedConfiguration Devices Data Sheet, Application Note 116: Configuring SRAM-Based LUT Devices, or Configuring Stratix & Stratix GX Devices.Altera has introduced additional enhanced configuration devices. Fordetails, please refer to the Process Change Notification PCN0506:Addition of Intel Flash Memory As Source For EPC4, EPC8 & EPC16Enhanced Configuration Devices and the Using Intel Flash Memory BasedEPC4, EPC8, and EPC16 white paper.Concurrent Configuration Using n-Bit PS ModesThe n-bit (n = 1, 2, 4, and 8) PS configuration mode allows enhancedconfiguration devices to concurrently configure SRAM-based devices ordevice chains. In addition, these devices do not have to be the samedevice family or density; they can be any combination of Altera SRAMbaseddevices. An individual enhanced configuration device DATA line isavailable for each targeted device. Each DATA line can also feed a daisychain of devices.The Quartus II software only allows the selection of n-bit PS configurationmodes. However, you can use these modes to configure any number ofdevices from 1 to 8. When configuring SRAM-based devices using n-bitPS modes, use Table 3–1 to select the appropriate configuration mode forthe fastest configuration times.3–2 Altera CorporationConfiguration Handbook, Volume 2 April 2007