Configuration Handbook - Kamami.pl

Configuring Stratix II & Stratix II GX DevicesTable 7–22. Dedicated Configuration Pins on the Stratix II & Stratix II GX Device (Part 2 of 10)Pin NameUser ModeConfigurationSchemePin TypeDescriptionPORSEL N/A All Input Dedicated input which selects between a PORtime of 12 ms or 100 ms. A logic high (1.5 V,1.8 V, 2.5 V, 3.3 V) selects a POR time of about12 ms and a logic low selects POR time ofabout 100 ms.The PORSEL input buffer is powered byV CCINT and has an internal 5-kΩ pull-downresistor that is always active. The PORSEL pinshould be tied directly to V CCPD or GND.nIO_PULLUP N/A All Input Dedicated input that chooses whether theinternal pull-up resistors on the user I/O pinsand dual-purpose I/O pins (nCSO, nASDO,DATA[7..0], nWS, nRS, RDYnBSY, nCS,CS, RUnLU, PGM[], CLKUSR, INIT_DONE,DEV_OE, DEV_CLR) are on or off before andduring configuration. A logic high (1.5 V, 1.8 V,2.5 V, 3.3 V) turns off the weak internal pull-upresistors, while a logic low turns them on.The nIO-PULLUP input buffer is powered byV CCPD and has an internal 5-kΩ pull-downresistor that is always active. ThenIO-PULLUP can be tied directly to V CCPD oruse a 1-kΩ pull-up resistor or tied directly toGND.MSEL[3..0] N/A All Input 4-bit configuration input that sets the Stratix IIand Stratix II GX device configurationscheme. Refer to Table 7–1 for the appropriateconnections.These pins must be hard-wired to V CCPD orGND.The MSEL[3..0] pins have internal 5-kΩpull-down resistors that are always active.Altera Corporation 7–95May 2007 Stratix II Device Handbook, Volume 2