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Configuration Handbook - Kamami.pl

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Device <strong>Configuration</strong> PinsTable 8–21 describes the optional configuration pins. If these optionalconfiguration pins are not enabled in the Quartus II software, they areavailable as general-purpose user I/O pins. Therefore duringconfiguration they function as user I/O pins, which means they are tristatedwith weak pull-up resistors.Table 8–21. Optional <strong>Configuration</strong> PinsPin Name User Mode Pin Type DescriptionCLKUSR N/A if option is on. I/O ifoption is off.InputOptional user-sup<strong>pl</strong>ied clock input.Synchronizes the initialization of one ormore devices. This pin is enabled by turningon the Enable user-sup<strong>pl</strong>ied start-up clock(CLKUSR) option in the Quartus II softwareINIT_DONEDEV_OEDEV_CLRnN/A if option is on. I/O ifoption is off.N/A if option is on. I/O ifoption is off.N/A if option is on. I/O ifoption is off.Output open-drainInputInputStatus pin. Can be used to indicate whenthe device has initialized and is in usermode. When nCONFIG is low and during thebeginning of configuration, the INIT_DONEpin is tri-stated and pulled high due to anexternal 1-kΩ pull-up. Once the option bit toenable INIT_DONE is programmed into thedevice (during the first frame ofconfiguration data), the INIT_DONE pin willgo low. When initialization is com<strong>pl</strong>ete, theINIT_DONE pin will be released and pulledhigh and the FPGA enters user mode. Thus,the monitoring circuitry must be able todetect a low-to-high transition. This pin isenabled by turning on the EnableINIT_DONE output option in the Quartus IIsoftware.Optional pin that allows the user to overrideall tri-states on the device. When this pin isdriven low, all I/O pins are tri-stated; whenthis pin is driven high, all I/O pins behave asprogrammed. This pin is enabled by turningon the Enable device-wide output enable(DEV_OE) option in the Quartus II software.Optional pin that allows you to override allclears on all device registers. When this pinis driven low, all registers are cleared; whenthis pin is driven high, all registers behaveas programmed. This pin is enabled byturning on the Enable device-wide reset(DEV_CLRn) option in the Quartus IIsoftware.8–68 Altera Corporation<strong>Configuration</strong> <strong>Handbook</strong>, Volume 1 August 2005

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