Configuration Handbook - Kamami.pl

Passive Serial ConfigurationfThe value of the weak pull-up resistors on the I/O pins that are on beforeand during configuration can be found in the Operating Conditions tableof the appropriate device family data sheet.The configuration cycle consists of 3 stages: reset, configuration, andinitialization. While nCONFIG or nSTATUS are low, the device is in reset.To initiate configuration in this scheme, the download cable generates alow-to-high transition on the nCONFIG pin.1 VCCINT and VCCIO pins on the banks where the configurationand JTAG pins reside need to be fully powered to theappropriate voltage levels in order to begin the configurationprocess.When nCONFIG goes high, the device comes out of reset and releases theopen-drain nSTATUS pin, which is then pulled high by an external 1-kΩpull-up resistor. Once nSTATUS is released the FPGA is ready to receiveconfiguration data and the configuration stage begins. The programminghardware or download cable then places the configuration data one bit ata time on the device’s DATA0 pin. The configuration data is clocked intothe target device until CONF_DONE goes high.When using a download cable, setting the Auto-Restart Configuration AfterError option does not affect the configuration cycle because you mustmanually restart configuration in the Quartus II software when an erroroccurs. Additionally, the Enable user-supplied start-up clock (CLKUSR)option has no affect on the device initialization since this option isdisabled in the SOF when programming the FPGA using the Quartus IIprogrammer and download cable. Therefore, if you turn on the CLKUSRoption, you do not need to provide a clock on CLKUSR when you areconfiguring the FPGA with the Quartus II programmer and a downloadcable. Figure 8–13 shows PS configuration for Mercury, APEX 20K(2.5 V), ACEX 1K, and FLEX 10K devices using a USB Blaster,MasterBlaster, ByteBlaster II or ByteBlasterMV cable.8–30 Altera CorporationConfiguration Handbook, Volume 1 August 2005