Configuration Handbook - Kamami.pl

Passive Serial ConfigurationfThe value of the internal pull-up resistors on the enhanced configurationdevices can be found in the Operating Conditions table of the EnhancedConfiguration Devices (EPC4, EPC8, & EPC16) Data Sheet or theConfiguration Devices for SRAM-based LUT Devices Data Sheet.When using enhanced configuration devices, nCONFIG of the device canbe connected to nINIT_CONF of the configuration device, which allowsthe INIT_CONF JTAG instruction to initiate device configuration. ThenINIT_CONF pin does not need to be connected if its functionality is notused. An internal pull-up resistor on the nINIT_CONF pin is alwaysactive in enhanced configuration devices, which means an externalpull-up resistor should not be used if nCONFIG is tied to nINIT_CONF.Upon power-up, the Stratix II and Stratix II GX devices go through aPOR. The POR delay is dependent on the PORSEL pin setting. WhenPORSEL is driven low, the POR time is approximately 100 ms. If PORSELis driven high, the POR time is approximately 12 ms. During POR, thedevice will reset, hold nSTATUS low, and tri-state all user I/O pins. Theconfiguration device also goes through a POR delay to allow the powersupply to stabilize. The POR time for EPC2 devices is 200 ms (maximum).The POR time for enhanced configuration devices can be set to either100 ms or 2 ms, depending on its PORSEL pin setting. If the PORSEL pinis connected to GND, the POR delay is 100 ms. If the PORSEL pin isconnected to V CC , the POR delay is 2 ms. During this time, theconfiguration device drives its OE pin low. This low signal delaysconfiguration because the OE pin is connected to the target device’snSTATUS pin.1 When selecting a POR time, you need to ensure that the devicecompletes power-up before the enhanced configuration deviceexits POR. Altera recommends that you choose a POR time forthe Stratix II or Stratix II GX device of 12 ms, while selecting aPOR time for the enhanced configuration device of 100 ms.When both devices complete POR, they release their open-drain OE ornSTATUS pin, which is then pulled high by a pull-up resistor. Once thedevice successfully exits POR, all user I/O pins continue to be tri-stated.If nIO_pullup is driven low during power-up and configuration, theuser I/O pins and dual-purpose I/O pins will have weak pull-upresistors which are on (after POR) before and during configuration. IfnIO_pullup is driven high, the weak pull-up resistors are disabled.fThe value of the weak pull-up resistors on the I/O pins that are on beforeand during configuration can be found in the DC & SwitchingCharacteristics chapter in the Stratix II Device Handbook and theStratix II GX Device Handbook.7–56 Altera CorporationStratix II Device Handbook, Volume 2 May 2007