Configuration Handbook - Kamami.pl

Configuring Stratix & Stratix GX DevicesFigure 11–9. PS Timing Waveform for Stratix & Stratix GX Devices Note (1)t CFGt CF2ST1nCONFIGt CF2CKt STATUSnSTATUS (2)CONF_DONE (3)DCLKt CF2CDt CF2ST0t CLKt CH t CLt DH(4)t ST2CKHigh-ZDATAUser I/OBit 0 Bit 1 Bit 2 Bit 3 Bit nt DSU(4)User ModeINIT_DONEt CD2UMNotes to Figure 11–9:(1) The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS, andCONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.(2) Upon power-up, the Stratix II device holds nSTATUS low for the time of the POR delay.(3) Upon power-up, before and during configuration, CONF_DONE is low.(4) DCLK should not be left floating after configuration. It should be driven high or low, whichever is convenient.DATA[] is available as user I/Os after configuration and the state of these pins depends on the dual-purpose pinsettings.FPP ConfigurationParallel configuration of Stratix and Stratix GX devices meets thecontinuously increasing demand for faster configuration times. Stratixand Stratix GX devices can receive byte-wide configuration data per clockcycle, and guarantee a configuration time of less than 100 ms with a 100-MHz configuration clock. Stratix and Stratix GX devices supportprogramming data bandwidth up to 800 megabits per second (Mbps) inthis mode. You can use parallel configuration with an EPC16, EPC8, orEPC4 device, or a microprocessor.This section discusses the following schemes for FPP configuration inStratix and Stratix GX devices:■■FPP Configuration Using an Enhanced Configuration DeviceFPP Configuration Using a MicroprocessorAltera Corporation 11–21July 2005 Stratix Device Handbook, Volume 2