Configuration Handbook - Kamami.pl

Configuring Stratix II & Stratix II GX DevicesfFor more information on configuring multiple Altera devices in the sameconfiguration chain, refer to Configuring Mixed Altera device Chains in theConfiguration Handbook.PS Configuration TimingFigure 7–20 shows the timing waveform for PS configuration when usinga MAX II device as an external host.Figure 7–20. PS Configuration Timing Waveform Note (1)t CFGt CF2ST1nCONFIGt CF2CKt STATUSnSTATUS (2)CONF_DONE (3)DCLKt CF2CDt CF2ST0t CLKt CH t CLt DH(4)t ST2CKHigh-ZDATAUser I/OBit 0 Bit 1 Bit 2 Bit 3 Bit nt DSU(4)User ModeINIT_DONENotes to Figure 7–20:(1) The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS andCONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.(2) Upon power-up, the Stratix II or Stratix II GX device holds nSTATUS low for the time of the POR delay.(3) Upon power-up, before and during configuration, CONF_DONE is low.(4) DCLK should not be left floating after configuration. It should be driven high or low, whichever is more convenient.DATA[0] is available as a user I/O pin after configuration and the state of this pin depends on the dual-purpose pinsettings.t CD2UMTable 7–15 defines the timing parameters for Stratix II and Stratix II GXdevices for PS configuration.Table 7–15. PS Timing Parameters for Stratix II & Stratix II GX Devices (Part 1 of 2) Note (1)Symbol Parameter Min Max Unitst CF2CD nCONFIG low to CONF_DONE low 800 nst CF2ST0 nCONFIG low to nSTATUS low 800 nsAltera Corporation 7–53May 2007 Stratix II Device Handbook, Volume 2