Configuration Handbook - Kamami.pl

Configuring APEX II DevicesWhen nSTATUS is pulled high, OE of the configuration device also goeshigh and the configuration device clocks data out serially to the FPGAusing its internal oscillator. The APEX II device receives configurationdata on its DATA0 pin and the clock is received on the DCLK pin. Data islatched into the FPGA on the rising edge of DCLK.After the FPGA has received all configuration data successfully, it releasesthe open-drain CONF_DONE pin, which is pulled high by a pull-upresistor. Since CONF_DONE is tied to the configuration device’s nCS pin,the configuration device is disabled when CONF_DONE goes high.Enhanced configuration and EPC2 devices have an optional internal pullupresistor on the nCS pin. This option is available in the Quartus IIsoftware from the General tab of the Device & Pin Options dialog box.If this internal pull-up is not used, an external 1-kΩ pull-up resistor on thenCS/CONF_DONE line is required. A low-to-high transition onCONF_DONE indicates configuration is complete and initialization of thedevice can begin.In APEX II devices, the initialization clock source is either the APEX IIinternal oscillator (typically 10 MHz) or the optional CLKUSR pin. Bydefault, the internal oscillator is the clock source for initialization. If theinternal oscillator is used, the APEX II device will supply itself withenough clock cycles for proper initialization. You also have the flexibilityto synchronize initialization of multiple devices by using the CLKUSRoption. You can turn on the Enable user-supplied start-up clock (CLKUSR)option in the Quartus II software from the General tab of the Device &Pin Options dialog box. Supplying a clock on CLKUSR will not affect theconfiguration process. After all configuration data is accepted andCONF_DONE goes high, APEX II devices require 40 clock cycles toproperly initialize.Altera Corporation 6–5August 2005 Configuration Handbook, Volume 1