Configuration Handbook - Kamami.pl

Configuring Stratix III DevicesIf CONF_DONE is high, the software indicates that configuration wassuccessful. After the configuration bitstream is transmitted serially viathe JTAG TDI port, the TCK port is clocked an additional 1,094 cycles toperform device initialization.Stratix III devices have dedicated JTAG pins that always function as JTAGpins. Not only can you perform JTAG testing on Stratix III devices beforeand after, but also during configuration. While other device families donot support JTAG testing during configuration, Stratix III devices supportthe bypass, id code, and sample instructions during configurationwithout interrupting configuration. All other JTAG instructions may onlybe issued by first interrupting configuration and reprogramming I/Opins using the CONFIG_IO instruction.The CONFIG_IO instruction allows I/O buffers to be configured via theJTAG port and when issued, interrupts configuration. This instructionallows you to perform board-level testing prior to configuring theStratix III device or waiting for a configuration device to completeconfiguration. Once configuration has been interrupted and JTAG testingis complete, you must reconfigure the part via JTAG (PULSE_CONFIGinstruction) or by pulsing nCONFIG low.The chip-wide reset (DEV_CLRn) and chip-wide output enable (DEV_OE)pins on Stratix III devices do not affect JTAG boundary-scan orprogramming operations. Toggling these pins does not affect JTAGoperations (other than the usual boundary-scan operation).When designing a board for JTAG configuration of Stratix III devices,consider the dedicated configuration pins. Table 11–13 shows how thesepins should be connected during JTAG configuration.Table 11–13. Dedicated Configuration Pin Connections During JTAGConfiguration (Part 1 of 2)SignalnCEnCEOMSELDescriptionOn all Stratix III devices in the chain, nCE should be driven lowby connecting it to ground, pulling it low via a resistor, or drivingit by some control circuitry. For devices that are also inmulti-device FPP, AS, or PS configuration chains, the nCE pinsshould be connected to GND during JTAG configuration or JTAGconfigured in the same order as the configuration chain.On all Stratix III devices in the chain, you can leave nCEO floatingor connected to the nCE of the next device.These pins must not be left floating. These pins supportwhichever non-JTAG configuration is used in production. If youonly use JTAG configuration, tie these pins to ground.Altera Corporation 11–69May 2007 Stratix III Device Handbook, Volume 1