Configuration Handbook - Kamami.pl

Configuring Stratix II & Stratix II GX DevicesPPA Configuration TimingFigure 7–33 shows the timing waveform for the PPA configurationscheme using a microprocessor.Figure 7–33. Stratix II & Stratix II GX PPA Configuration Timing Waveform Using nWS Note (1)t CFGt STATUSnCONFIGnSTATUS (2)CONF_DONE (3)DATA[7..0]t CF2ST1t DSUt CSSUt CSHt CD2UMByte 0 Byte 1Byte n − 1Byte n(5)(4) CS(4) nCSnWSRDYnBSY(5)t t CF2WSDH(5)t WSP(5)t RDY2WS(5)t WS2Bt BUSYt CF2ST0t CF2CDUser I/OsHigh-ZHigh-ZUser-ModeINIT_DONENotes to Figure 7–33:(1) The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS andCONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.(2) Upon power-up, Stratix II and Stratix II GX devices hold nSTATUS low for the time of the POR delay.(3) Upon power-up, before and during configuration, CONF_DONE is low.(4) The user can toggle nCS or CS during configuration if the design meets the specification for t CSSU , t WSP , and t CSH .(5) DATA[7..0], CS, nCS, nWS, nRS, and RDYnBSY are available as user I/O pins after configuration and the state oftheses pins depends on the dual-purpose pin settings.Altera Corporation 7–81May 2007 Stratix II Device Handbook, Volume 2