Configuration Handbook - Kamami.pl

Pin InformationTable 5–20. EPC2, EPC1 & EPC1441 Pin Functions During Configuration (Part 2 of 4)Pin Name8-PinPDIP (1)Pin Number20-PinPLCC32-PinTQFP (2)Pin TypeOE 3 8 7 Open-DrainBidirectionalDescriptionOutput enable (active high) and reset (activelow). The OE pin connects to the nSTAUTUS ofthe FPGA.A low logic level resets the address counter. Ahigh logic level enables DATA and the addresscounter to count. If this pin is low (reset) duringconfiguration, the internal oscillator becomesinactive and DCLK drives low. See “ErrorDetection Circuitry” on page 5–12.The OE pin has an internal programmable 1-kΩresistor in EPC2 devices. If internal pull-upresistors are use, external pull-up resistorsshould not be used on these pins. The internalpull-up resistors can be disabled through theDisable nCS and OE pull-ups onconfiguration device option.nCS 4 9 10 Input Chip select input (active low). The nCS pinconnects to the CONF_DONE of the FPGA.A low input allows DCLK to increment theaddress counter and enables DATA to drive out.If the EPC2 or EPC1 is reset (OE pulled low)while nCS is low, the device initializes as themaster device in a configuration chain. If theEPC2 or EPC1 device is reset (OE pulled low)while nCS is high, the device initializes as a slavedevice in the chain.The nCS pin has an internal programmable 1-kΩresistor in EPC2 devices. If internal pull-upresistors are use, external pull-up resistorsshould not be used on these pins.The internalpull-up resistors can be disabled through theDisable nCS and OE pull-ups onconfiguration device option.5–28 Altera CorporationConfiguration Handbook, Volume 2 April 2007