Configuration Handbook - Kamami.pl

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Configuring APEX 20KE & APEX 20KC DevicesThe enhanced configuration devices also support parallel configurationof up to eight devices. The n-bit (n = 1, 2, 4, or 8) PS configuration modeallows enhanced configuration devices to concurrently configure FPGAsor a chain of FPGAs. In addition, these devices do not have to be the samedevice family or density; they can be any combination of Altera FPGAs.An individual enhanced configuration device DATA line is available foreach targeted FPGA. Each DATA line can also feed a daisy chain of FPGAs.Figure 7–3 shows how to concurrently configure multiple devices usingan enhanced configuration device.Altera Corporation 7–11August 2005 Configuration Handbook, Volume 1
Passive Serial ConfigurationFigure 7–3. Concurrent PS Configuration of Multiple Devices Using an Enhanced Configuration Device(2)10 kΩV CC(2)(1) V CC V CC (1)N.C.APEX 20KE orAPEX 20KC Device 1nCEOMSEL1MSEL0DCLKDATA0nSTATUSCONF_DONEnCONFIGnCE10 kΩ (4) (4) 10 kΩEnhancedConfigurationDeviceDCLKDATA0DATA1DATA[2..6]OE (4)nCS (4)GNDN.C.APEX 20KE orAPEX 20KC Device 2DCLKDATA0nSTATUSCONF_DONEnCEO nCONFIGGND(3)nINIT_CONF (2)DATA 7MSEL1MSEL0nCEGNDGNDN.C.APEX 20KE orAPEX 20KE Device 8nCEODCLKDATA0nSTATUSCONF_DONEnCONFIGMSEL1MSEL0nCEGNDGNDNotes to Figure 7–3:(1) The pull-up resistor should be connected to the same supply voltage as the configuration device.(2) The nINIT_CONF pin (available on enhanced configuration devices and EPC2 devices only) does not need to beconnected if its functionality is not used. If nINIT_CONF is not used or not available (e.g., on EPC1 devices),nCONFIG must be pulled to V CC through a 10-kΩ resistor. For APEX 20KE devices, nCONFIG should be pulled up toV CCINT . For APEX 20KC devices, nCONFIG should be connected to the same supply voltage as the configurationdevice.(3) The nINIT_CONF pin has an internal pull-up resistor to 3.3 V that is always active. Since a 10-kΩ pull-up to V CCINTis required to successfully configure APEX 20KE devices, you need to isolate the 1.8-V V CCINT from the configurationdevice’s 3.3-V supply. To isolate the 1.8-V and 3.3-V power supplies, add a diode between the APEX 20KE device’snCONFIG pin and the configuration device’s nINIT_CONF pin. Select a diode with a threshold voltage (V T ) less thanor equal to 0.7 V. The diode will make the nINIT_CONF pin an open-drain pin; the pin will only be able to drive lowor tri-state. If nINIT_CONF is not used or not available (e.g., on EPC1 devices), this diode is not needed. The diodeis also not needed when configuring APEX 20KC devices.(4) The enhanced configuration devices’ and EPC2 devices’ OE and nCS pins have internal programmable pull-upresistors. For successful configuration of APEX 20KE and APEX 20KC devices using EPC2 devices, you should useexternal 10-kΩ pull-up resistors. If internal pull-up resistors on the enhanced configuration device are used, externalpull-up resistors should not be used on these pins. The internal pull-up resistors are used by default in theQuartus II software. To turn off the internal pull-up resistors, check the Disable nCS and OE pull-up resistors onconfiguration device option when generating programming files.7–12 Altera CorporationConfiguration Handbook, Volume 1 August 2005
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Configuration HandbookPreliminary I
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ContentsVolume I...................
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Altera FPGAsPreliminary Information
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IntroductionAll configuration schem
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Device Configuration Overview for P
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Selecting a Configuration SchemeSel
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Selecting a Configuration SchemePas
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IntroductionfFor information on enh
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Configuration FeaturesUse the data
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Configuration FeaturesStratix III d
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Configuration Features5. Select Add
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Configuration FeaturesV CCPGM PinsS
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Fast Passive Parallel Configuration
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Fast Active Serial Configuration (S
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Passive Serial ConfigurationPS Conf
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Passive Serial ConfigurationAn opti
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Passive Serial ConfigurationDCLK, D
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Passive Serial ConfigurationFigure
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Passive Serial Configuration1 To be
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Passive Serial Configuration1 If yo
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Passive Serial ConfigurationThe enh
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Passive Serial ConfigurationThe Qua
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Passive Serial Configuration1 You c
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Passive Serial Configurationoption
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Passive Serial ConfigurationIf you
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JTAG ConfigurationJTAGConfiguration
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JTAG ConfigurationFigure 11-29. JTA
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JTAG ConfigurationTable 11-13. Dedi
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JTAG ConfigurationAfter the first d
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Device Configuration PinsTable 11-1
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ConclusionConclusionDocumentRevisio
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Introduction1 For more information
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Configuration FeaturesTable 7-3. St
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Configuration Features1 When using
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Configuration Features6. Select the
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Configuration FeaturesV CCPD PinsSt
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Configuration Featuresthan 00X0 (MS
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Active Serial Configuration (Serial
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Passive Serial ConfigurationTable 7
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Passive Serial ConfigurationfThe va
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Passive Serial Configurationpulled
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Passive Serial ConfigurationIf the
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Passive Serial Configurationsoftwar
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Passive Serial Configurationconfigu
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Passive Serial ConfigurationUpon po
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Passive Serial ConfigurationIn addi
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Passive Parallel Asynchronous Confi
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JTAG ConfigurationJTAGConfiguration
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JTAG ConfigurationFigure 7-35. JTAG
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JTAG ConfigurationTable 7-20. Dedic
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JTAG ConfigurationAfter the first d
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Device Configuration PinsDeviceConf
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ConclusionConclusionDocumentRevisio
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Device Configuration Overview■The
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Device Configuration Overviewrelate
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Configuration File SizeTDO & nCEO P
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Configuration SchemesPS Configurati
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Configuration SchemesFigure 11-2. S
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Configuration SchemesRestart Config
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Configuration SchemesTable 11-7 sho
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Configuration SchemesFigure 11-6. M
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Configuration SchemesTable 11-8. PS
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Configuration SchemesFPP Configurat
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Configuration SchemesDo not drive C
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Configuration Schemesdefault, the I
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Configuration SchemesFigure 11-13.
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Configuration SchemesTable 11-9. FP
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Configuration Schemesbe monitored,
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Configuration SchemesPPA Configurat
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Configuration SchemesTable 11-10 de
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Configuration SchemesDuring JTAG co
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Configuration SchemesJTAG-chain dev
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Configuration SchemesfFor more info
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Configuration SchemesProgram FlowTh
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Configuration Schemessend JTAG data
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Configuration SchemesTable 11-14. R
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Cyclone II Configuration OverviewTa
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Configuration Data CompressionAltho
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PS ConfigurationPS ConfigurationYou
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PS ConfigurationConfiguration Stage
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PS Configurationdevice also pulls n
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PS ConfigurationYou must connect al
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PS ConfigurationPS Configuration Ti
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PS ConfigurationfAll information in
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PS ConfigurationUpon power-up, the
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PS ConfigurationnCONFIG is low and
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PS ConfigurationFigure 13-14. Multi
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PS ConfigurationnCONFIG low for at
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PS ConfigurationDATA3, you can leav
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PS ConfigurationPS Configuration Us
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PS ConfigurationIn addition, becaus
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PS Configurationthe five common sig
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JTAG ConfigurationA device operatin
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JTAG Configurationenables the progr
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JTAG ConfigurationFigure 13-23. JTA
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JTAG Configuration1 The Quartus II
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JTAG Configurationfeature. To use t
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Device Configuration PinsReconfigur
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ConclusionTable 13-13 describes the
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Document Revision HistoryDocumentRe
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Device Configuration OverviewYou ca
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Data CompressionWhen you enable com
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Data CompressionCompression can als
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Configuration SchemesConfigurationS
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Configuration Schemesinternal oscil
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Configuration SchemesFigure 13-6. C
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Configuration SchemesFigure 13-7. C
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Configuration SchemesASDI and nCS s
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Configuration SchemesYou can progra
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Configuration SchemesWhen configuri
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Configuration SchemesFigure 13-18 s
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Configuration Schemesattempt JTAG c
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Configuration Schemes1 If V CCIO is
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Configuration Schemes1 Both JTAG co
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Configuration Schemessend JTAG data
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Configuration SchemesTable 13-9. Re
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Document Revision History13-52 Alte
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Passive Serial Configurationinterna
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Passive Serial ConfigurationHandsha
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Passive Serial ConfigurationIf the
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Passive Serial Configurationoption,
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Device Configuration PinsTable 7-9.
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APEX 20KE Power SequencingThese gui
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APEX 20KE Power SequencingUse these
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APEX 20KE Power Sequencing7-70 Alte
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Introductionsuccessfully. Toggling
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Passive Serial ConfigurationThe fol
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JTAG ConfigurationTable 8-18 explai
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JTAG ConfigurationMercury, APEX 20K
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JTAG ConfigurationOther Altera devi
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Device Configuration Pins8-70 Alter
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FPGA Configuration DevicesPrelimina
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Choosing a Configuration DevicefFor
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1-4 Altera CorporationConfiguration
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Functional Description■■■■
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Functional DescriptionFigure 2-1. E
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Functional DescriptionIn addition t
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Functional DescriptionFast Passive
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Functional DescriptionThe configura
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Functional DescriptionTable 2-3 sum
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Enhanced Configuration Devices (EPC
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3. Altera EnhancedConfiguration Dev
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4. Serial ConfigurationDevices (EPC
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Software SettingsPreliminary Inform
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IntroductionThe Configuration schem
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IntroductionFigure 6-3. Configurati
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Generating Configuration FilesYou c
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8. Configuring Mixed AlteraFPGA Cha
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Configuring Mixed Altera FPGA Chain
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9. Combining DifferentConfiguration
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Combining Different Configuration S
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10. Using Flash Memory toConfigure
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Debugging Suggestions■■To check
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Debugging SuggestionsUsing JTAG Con
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Document Revision History11-8 Alter
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