Configuration Handbook - Kamami.pl

Device Configuration PinsTable 7–22. Dedicated Configuration Pins on the Stratix II & Stratix II GX Device (Part 7 of 10)Pin NameUser ModeConfigurationSchemeDCLK N/A Synchronousconfigurationschemes (PS,FPP, AS)Pin TypeInput (PS,FPP) Output(AS)DescriptionIn PS and FPP configuration, DCLK is theclock input used to clock data from an externalsource into the target device. Data is latchedinto the device on the rising edge of DCLK.In AS mode, DCLK is an output from theStratix II or Stratix II GX device that providestiming for the configuration interface. In ASmode, DCLK has an internal pull-up resistor(typically 25 kΩ) that is always active.DATA0 I/O PS, FPP, PPA,ASInputIn PPA mode, DCLK should be tied high to V CCto prevent this pin from floating.After configuration, this pin is tri-stated. Inschemes that use a configuration device,DCLK will be driven low after configuration isdone. In schemes that use a control host,DCLK should be driven either high or low,whichever is more convenient. Toggling thispin after configuration does not affect theconfigured device.Data input. In serial configuration modes,bit-wide configuration data is presented to thetarget device on the DATA0 pin.The V IH and V IL levels for this pin aredependent on the input buffer selected by theVCCSEL pin. Refer to the section “VCCSELPin” on page 7–10 for more information.In AS mode, DATA0 has an internal pull-upresistor that is always active.After configuration, DATA0 is available as auser I/O pin and the state of this pin dependson the Dual-Purpose Pin settings.After configuration, EPC1 and EPC1441devices tri-state this pin, while enhancedconfiguration and EPC2 devices drive this pinhigh.7–100 Altera CorporationStratix II Device Handbook, Volume 2 May 2007