12.07.2015 Views

Configuration Handbook - Kamami.pl

Configuration Handbook - Kamami.pl

Configuration Handbook - Kamami.pl

SHOW MORE
SHOW LESS

You also want an ePaper? Increase the reach of your titles

YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.

Debugging Suggestions■■To check if the FPGA has started accepting configuration data, youcan monitor the INIT_DONE pin. The INIT_DONE pin is an optionalpin and can be turned on in the Quartus II software through theEnable INIT_DONE output option. The INIT_DONE pin is an opendrainoutput and requires an external pull-up to V CC . Therefore,when nCONFIG is low and during the beginning of configuration, theINIT_DONE will be at a logic high level. After the option bit to enablethe INIT_DONE pin is programmed into the FPGA (during the firstframe of configuration data), the INIT_DONE pin will go low. Thetransition of INIT_DONE from high to low signals that the FPGA hasindeed begun configuration and started to accept configuration data.If the INIT_DONE pin remains high, the FPGA has not received theproper configuration file header to indicate the beginning ofconfiguration data.If the configuration device or external host has sent all configurationdata and CONF_DONE has not gone high, ensure CONF_DONE has apull-up to V CC and that it is not grounded or driven low on yourboard.Multi-Device <strong>Configuration</strong> Chains■■You should combine each device’s SOF into one configuration filethrough the Convert Programming Files dialog box in the Quartus IIsoftware. For more information, refer to the <strong>Configuration</strong> File FormatsChapter.When generating the configuration file, ensure the configurationfiles are in the same order as the devices on the board.Using an External Host (e.g., Microprocessor or CPLD)■■■If using a Raw Binary File (.rbf) to configure your Altera FPGA(s),make sure the least significant bit (LSB) of each byte is sent first. If thefile is sent in the wrong order, this will cause a configuration error.Scope the DATA and DCLK or nWS signals to check that all timingparameters are met as specified in the tables in the appropriatedevice family chapter.If using passive parallel asynchronous (PPA), make sure nRS is notleft floating. This pin should be driven high if it is not used,otherwise configuration errors can occur.11–4 Altera Corporation<strong>Configuration</strong> <strong>Handbook</strong>, Volume 2 April 2007

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!