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Configuring APEX II DevicesfFor more information on configuring multiple Altera devices in the sameconfiguration chain, refer to Configuring Mixed Altera FPGA Chainschapter 8 in volume 2 of the Configuration Handbook.Figure 6–8 shows the timing waveform for the PS configuration schemeusing a configuration device.Figure 6–8. APEX II PS Configuration Using a Configuration Device Timing WaveformnINIT_CONF or VCC/nCONFIGOE/nSTATUSnCS/CONF_DONEDCLKDATAt PORt CHt DSU t CLt OEZXD D D D0 1 2 3 D nUser I/OINIT_DONEt DHt COTri-StateTri-StateUser ModeNote to Figure 6–8:(1) APEX II devices enter user-mode 40 clock cycles after CONF_DONE goes high. The initialization clock can come fromthe APEX II internal oscillator or the CLKUSR pin.(1)ffFor timing information, refer to the Enhanced Configuration Devices(EPC4, EPC8, and EPC16) Data Sheet or the Configuration Devices forSRAM-based LUT Devices Data Sheet in the Configuration Handbook.Device configuration options and how to create configuration files arediscussed further in Section II, Software Settings, chapter 6 and 7 involume 2 of the Configuration Handbook.PS Configuration Using a MicroprocessorIn the PS configuration scheme, an intelligent host (e.g., a microprocessoror CPLD) can transfer configuration data from a storage device (e.g., flashmemory) to the target APEX II devices. Configuration data can be storedin RBF, HEX, or TTF format. Figure 6–9 shows the configuration interfaceconnections between the APEX II device and a microprocessor for singledevice configuration.Altera Corporation 6–17August 2005 Configuration Handbook, Volume 1