Configuration Handbook - Kamami.pl

Configuring Stratix & Stratix GX DevicesFigure 11–5. PS Configuration Circuit with a Download CableV CC (1) V CC (1)V CC(2) 10 kΩ (2)V CC (1)10 kΩ (2)10 kΩGNDStratix orStratix GX DeviceMSEL2MSEL1MSEL0nCEDCLKDATA0nCONFIGCONF_DONEnSTATUSnCEON.C.V CC (1)10 kΩV CC (1)10 kΩPin 1Download Cable10-Pin Male Header(PS Mode)V CCGNDVIO (3)ShieldGNDNotes to Figure 11–5:(1) You should connect the pull-up resistor to the same supply voltage as the MasterBlaster (VIO pin) or ByteBlasterMVcable.(2) The pull-up resistors on the DATA0 and DCLK pins are only needed if the download cable is the only configurationscheme used on the board. This is to ensure that the DATA0 and DCLK pins are not left floating after configuration.For example, if the design also uses a configuration device, the pull-up resistors on the DATA0 and DCLK pins arenot necessary.(3) Pin 6 of the header is a V IO reference voltage for the MasterBlaster output driver. V IO should match the device’sV CCIO . This pin is a no-connect pin for the ByteBlasterMV header.You can use programming hardware to configure multiple Stratix andStratix GX devices by connecting each device’s nCEO pin to thesubsequent device’s nCE pin. All other configuration pins are connectedto each device in the chain.Because all CONF_DONE pins are tied together, all devices in the chaininitialize and enter user mode at the same time. In addition, because thenSTATUS pins are tied together, the entire chain halts configuration if anydevice detects an error. In this situation, the Quartus II software mustrestart configuration; the Auto-Restart Configuration on Frame Erroroption does not affect the configuration cycle.Figure 11–6 shows how to configure multiple Stratix and Stratix GXdevices with a MasterBlaster or ByteBlasterMV cable.Altera Corporation 11–15July 2005 Stratix Device Handbook, Volume 2