Configuration Handbook - Kamami.pl

Configuration SchemesFigure 13–18 shows the PS timing waveform for Cyclone FPGAs.Figure 13–18. PS Timing Waveform for Cyclone FPGAst CFGt CF2ST1nCONFIGt CF2CKt STATUSnSTATUS (1)CONF_DONE (2)t CF2CDt CF2ST0t ST2CKt CLKt CH t CLt DHDCLK (3)DATAUser I/OBit 0 Bit 1 Bit 2 Bit 3 Bit nt DSUTri-stated with internal pull-up resistor(4)User ModeINIT_DONENotes to Figure 13–18:(1) Upon power-up, the Cyclone FPGA holds nSTATUS low for about 100 ms.(2) Upon power-up and before configuration, CONF_DONE is low.(3) In user mode, DCLK should be driven high or low when using the PS configuration scheme. When using the ASconfiguration scheme, DCLK is a Cyclone output pin and should not be driven externally.(4) DATA should not be left floating after configuration. It should be driven high or low, whichever is more convenient.t CD2UMTable 13–5 contains the PS timing information for Cyclone FPGAs.Table 13–5. PS Timing Parameters for Cyclone Devices Note (1) (Part 1 of 2)Symbol Parameter Min Max Unitst CF2CD nCONFIG low to CONF_DONE low 800 nst CF2ST0 nCONFIG low to nSTATUS low 800 nst CF2ST1 nCONFIG high to nSTATUS high 40 (4) µst CFG nCONFIG low pulse width (2) 40 µst STATUS nSTATUS low pulse width 10 40 (4) µst CF2CK nCONFIG high to first rising edge on DCLK 40 µst ST2CK nSTATUS high to first rising edge on DCLK 1 µst DSU Data setup time before rising edge on DCLK 7 nst DH Data hold time after rising edge on DCLK 0 nst CH DCLK high time 7 ns13–30 Altera CorporationCyclone Device Handbook, Volume 1 January 2007