Configuration Handbook - Kamami.pl

Passive Serial ConfigurationPS Configuration Using a MicroprocessorIn the PS configuration scheme, an intelligent host (e.g., a microprocessoror CPLD) can transfer configuration data from a storage device (e.g., flashmemory) to the target Mercury, APEX 20K (2.5 V), ACEX 1K, andFLEX 10K devices. Configuration data can be stored in RBF, HEX, or TTFformat. Figure 8–9 shows the configuration interface connectionsbetween the Mercury, APEX 20K (2.5 V), ACEX 1K, or FLEX 10K deviceand a microprocessor for single device configuration.Figure 8–9. Single Device PS Configuration Using a MicroprocessorMemoryADDR DATA0Microprocessor(1) VCC VCC (1)1 kΩ 1 kΩMercury, APEX 20K (2.5-V)ACEX 1K or FLEX 10K DeviceGNDMSEL0CONF_DONEnSTATUSnCEnCEODATA0nCONFIGDCLKMSEL1GNDN.C.Note to Figure 8–9:(1) Connect the pull-up resistor to a supply that provides an acceptable input signalfor the device.Upon power-up, the Mercury, APEX 20K (2.5 V), ACEX 1K, or FLEX 10Kdevice goes through a POR for approximately 5 µs. During POR, thedevice resets and holds nSTATUS low, and tri-states all user I/O pins.Once the FPGA successfully exits POR, all user I/O pins are tri-stated.Mercury, APEX 20K (2.5 V), ACEX 1K, and FLEX 10KE devices have weakpull-up resistors on the user I/O pins which are on before and duringconfiguration.fThe value of the weak pull-up resistors on the I/O pins that are on beforeand during configuration can be found in the Operating Conditions tableof the appropriate device family data sheet.The configuration cycle consists of three stages: reset, configuration, andinitialization. While nCONFIG or nSTATUS are low, the device is in reset.To initiate configuration, the microprocessor must generate a low-to-hightransition on the nCONFIG pin.8–20 Altera CorporationConfiguration Handbook, Volume 1 August 2005