Configuration Handbook - Kamami.pl

Fast Passive Parallel ConfigurationFigure 7–6. FPP Configuration Timing Waveform Notes (1), (2)t CFGt CF2ST1nCONFIGt CF2CKt STATUSnSTATUS (3)t CF2ST0t CLKCONF_DONE (4)t CF2CDDCLK(5)DATA[7..0]t CH t CLt DHt ST2CKHigh-ZByte 0 Byte 1 Byte 2 Byte 3 Byte n(5)User Modet DSUUser I/OUser ModeINIT_DONEt CD2UMNotes to Figure 7–6:(1) This timing waveform should be used when the decompression and design security feature are not used.(2) The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS, andCONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.(3) Upon power-up, the Stratix II or Stratix II GX device holds nSTATUS low for the time of the POR delay.(4) Upon power-up, before and during configuration, CONF_DONE is low.(5) DCLK should not be left floating after configuration. It should be driven high or low, whichever is more convenient.(6) DATA[7..0] are available as user I/O pins after configuration and the state of these pins depends on thedual-purpose pin settings.Table 7–9 defines the timing parameters for Stratix II and Stratix II GXdevices for FPP configuration when the decompression and the designsecurity features are not enabled.Table 7–9. FPP Timing Parameters for Stratix II & Stratix II GX Devices (Part 1 of 2) Notes (1), (2)Symbol Parameter Min Max Unitst CF2CD nCONFIG low to CONF_DONE low 800 nst CF2ST0 nCONFIG low to nSTATUS low 800 nst CFG nCONFIG low pulse width 2 µst STATUS nSTATUS low pulse width 10 100 (3) µst CF2ST1 nCONFIG high to nSTATUS high 100 (3) µst CF2CK nCONFIG high to first rising edge on DCLK 100 µst ST2CK nSTATUS high to first rising edge of DCLK 2 µs7–22 Altera CorporationStratix II Device Handbook, Volume 2 May 2007