Configuration Handbook - Kamami.pl

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Configuring Stratix & Stratix GX DevicesFigure 11–23. Embedded System Block DiagramEmbedded Systemto/from ByteBlasterMVTDITMSTCKTDOInterfaceLogic(Optional)TDIEmbeddedProcessorControld[7..0]adr[19..0]208420820Controld[3..0]adr[19..0]Controld[7..0]adr[19..0]TMSTCKTDOEPROM orSystemMemoryTMSTCKTMSTCKTDITDOTDITDOAny JTAGDeviceMAX ® 9000,MAX 9000A,MAX 7000S,MAX 7000A,MAX 7000AE,or MAX 3000DeviceV CC V CC V CCTMSTCKTDITRSTnSTATUSCONF_DONEnCONFIGMSEL0MSEL1TDO nCETDIGND10 kΩ10 kΩAny Cyclone,FLEX 10K,FLEX 10KA,FLEX10KE,APEX 20K,or APEX 20KEDeviceTMSTCKMSEL1MSEL0(1)(1)(2)(2)(1)DATA0DCLKnCONFIGTDOCyclone FPGANotes to Figure 11–23:(1) Connect the nCONFIG, MSEL2, MSEL1, and MSEL0 pins to support a non-JTAG configuration scheme. If your designonly uses JTAG configuration, connect the nCONFIG pin to V CC and the MSEL2, MSEL1, and MSEL0 pins to ground.(2) Pull DATA0 and DCLK to either high or low.Both JTAG connection methods should include space for theMasterBlaster or ByteBlasterMV header connection. The header is usefulduring prototyping because it allows you to verify or modify the Stratixor Stratix GX device’s contents. During production, you can remove theheader to save cost.Altera Corporation 11–43July 2005 Stratix Device Handbook, Volume 2
Configuration SchemesProgram FlowThe Jam Player provides an interface for manipulating the IEEEStd. 1149.1 JTAG TAP state machine. The TAP controller is a 16-state statemachine that is clocked on the rising edge of TCK, and uses the TMS pin tocontrol JTAG operation in a device. Figure 11–24 shows the flow of anIEEE Std. 1149.1 TAP controller state machine.11–44 Altera CorporationStratix Device Handbook, Volume 2 July 2005
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Configuration HandbookPreliminary I
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ContentsVolume I...................
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Altera FPGAsPreliminary Information
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IntroductionAll configuration schem
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Device Configuration Overview for P
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Selecting a Configuration SchemeSel
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Selecting a Configuration SchemePas
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IntroductionfFor information on enh
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Configuration FeaturesUse the data
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Configuration FeaturesStratix III d
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Configuration Features5. Select Add
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Configuration FeaturesV CCPGM PinsS
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Fast Passive Parallel Configuration
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Fast Active Serial Configuration (S
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Passive Serial ConfigurationPS Conf
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Passive Serial ConfigurationAn opti
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Passive Serial ConfigurationDCLK, D
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Passive Serial ConfigurationFigure
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Passive Serial Configuration1 To be
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Passive Serial Configuration1 If yo
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Passive Serial ConfigurationThe enh
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Passive Serial ConfigurationThe Qua
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Passive Serial Configuration1 You c
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Passive Serial Configurationoption
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Passive Serial ConfigurationIf you
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JTAG ConfigurationJTAGConfiguration
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JTAG ConfigurationFigure 11-29. JTA
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JTAG ConfigurationTable 11-13. Dedi
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JTAG ConfigurationAfter the first d
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Device Configuration PinsTable 11-1
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ConclusionConclusionDocumentRevisio
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Introduction1 For more information
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Configuration FeaturesTable 7-3. St
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Configuration Features1 When using
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Configuration Features6. Select the
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Configuration FeaturesV CCPD PinsSt
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Configuration Featuresthan 00X0 (MS
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Active Serial Configuration (Serial
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Passive Serial ConfigurationTable 7
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Passive Serial ConfigurationfThe va
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Passive Serial Configurationpulled
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Passive Serial ConfigurationIf the
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Passive Serial Configurationsoftwar
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Passive Serial Configurationconfigu
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Passive Serial ConfigurationUpon po
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Passive Serial ConfigurationIn addi
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Passive Parallel Asynchronous Confi
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JTAG ConfigurationJTAGConfiguration
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JTAG ConfigurationFigure 7-35. JTAG
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JTAG ConfigurationTable 7-20. Dedic
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JTAG ConfigurationAfter the first d
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Device Configuration PinsDeviceConf
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Page 195 and 196: Device Configuration PinsTable 7-22
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Page 205 and 206: Device Configuration Overview■The
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Page 209 and 210: Configuration File SizeTDO & nCEO P
Page 211 and 212: Configuration SchemesPS Configurati
Page 213 and 214: Configuration SchemesFigure 11-2. S
Page 215 and 216: Configuration SchemesRestart Config
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Page 219 and 220: Configuration SchemesFigure 11-6. M
Page 221 and 222: Configuration SchemesPS Configurati
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Page 267 and 268: Configuration Data CompressionAltho
Page 269 and 270: Active Serial Configuration (Serial
Page 285 and 286: PS ConfigurationPS ConfigurationYou
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PS ConfigurationUpon power-up, the
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PS ConfigurationnCONFIG is low and
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PS ConfigurationFigure 13-14. Multi
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PS ConfigurationnCONFIG low for at
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PS ConfigurationDATA3, you can leav
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PS ConfigurationPS Configuration Us
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PS ConfigurationIn addition, becaus
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PS Configurationthe five common sig
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JTAG ConfigurationA device operatin
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JTAG Configurationenables the progr
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JTAG ConfigurationFigure 13-23. JTA
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JTAG Configuration1 The Quartus II
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JTAG Configurationfeature. To use t
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Device Configuration PinsReconfigur
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ConclusionTable 13-13 describes the
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Document Revision HistoryDocumentRe
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Device Configuration OverviewYou ca
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Data CompressionWhen you enable com
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Data CompressionCompression can als
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Configuration SchemesConfigurationS
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Configuration Schemesinternal oscil
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Configuration SchemesFigure 13-6. C
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Configuration SchemesFigure 13-7. C
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Configuration SchemesASDI and nCS s
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Configuration SchemesYou can progra
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Configuration SchemesWhen configuri
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Configuration SchemesFigure 13-12.
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Configuration SchemesPS Configurati
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Configuration SchemesFigure 13-18 s
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Configuration Schemesattempt JTAG c
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Configuration Schemes1 If V CCIO is
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Configuration Schemes1 Both JTAG co
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Configuration Schemessend JTAG data
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Configuration SchemesTable 13-9. Re
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Document Revision History13-52 Alte
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Passive Serial Configurationinterna
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Passive Serial ConfigurationHandsha
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Passive Serial ConfigurationIf the
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Passive Serial Configurationoption,
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JTAG ConfigurationTable 6-6. PPA Ti
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JTAG ConfigurationDuring JTAG confi
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JTAG ConfigurationFigure 6-30. JTAG
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Device Configuration PinsfFor more
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Device Configuration PinsTable 6-9.
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Device Configuration PinsJTAG pins
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IntroductionTable 7-2 shows the app
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Passive Serial Configuration1 V CCI
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Passive Serial ConfigurationWhen CO
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Passive Serial ConfigurationfFor mo
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Passive Serial Configurationpulled
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Passive Serial ConfigurationYou can
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Passive Serial ConfigurationYou can
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Passive Parallel Synchronous Config
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JTAG ConfigurationTable 7-6. PPA Ti
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JTAG Configurationprogramming devic
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JTAG ConfigurationJTAG-chain device
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JTAG ConfigurationThe Jam Player pr
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APEX 20KE Power SequencingThese gui
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APEX 20KE Power SequencingUse these
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APEX 20KE Power Sequencing7-70 Alte
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Introductionsuccessfully. Toggling
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Passive Serial ConfigurationThe fol
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Passive Serial ConfigurationUpon po
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Passive Serial ConfigurationIn mult
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JTAG ConfigurationTable 8-18 explai
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JTAG ConfigurationMercury, APEX 20K
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JTAG ConfigurationOther Altera devi
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Device Configuration Pins8-70 Alter
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FPGA Configuration DevicesPrelimina
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Choosing a Configuration DevicefFor
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1-4 Altera CorporationConfiguration
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1-6 Altera CorporationConfiguration
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Functional Description■■■■
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Functional DescriptionFigure 2-1. E
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Functional DescriptionIn addition t
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Functional DescriptionFast Passive
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Functional DescriptionThe configura
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Functional DescriptionTable 2-3 sum
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Enhanced Configuration Devices (EPC
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3. Altera EnhancedConfiguration Dev
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4. Serial ConfigurationDevices (EPC
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5. Configuration Devices forSRAM-Ba
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Configuration Devices for SRAM-Base
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Software SettingsPreliminary Inform
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IntroductionThe Configuration schem
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IntroductionFigure 6-3. Configurati
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IntroductionTable 6-1. Configuratio
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Generating Configuration FilesYou c
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SRAM Object File (.sof)6. Click on
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Tabular Text File (.ttf)Tabular Tex
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8. Configuring Mixed AlteraFPGA Cha
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Configuring Mixed Altera FPGA Chain
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9. Combining DifferentConfiguration
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Combining Different Configuration S
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10. Using Flash Memory toConfigure
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Using Flash Memory to Configure FPG
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Board Layout Tips & Debugging Techn
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Debugging Suggestions■■To check
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Debugging SuggestionsUsing JTAG Con
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Document Revision History11-8 Alter
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