Configuration Handbook - Kamami.pl

Configuring APEX II DevicesPS Configuration Using a Download CableIn this section, the generic term “download cable” includes the AlteraUSB Blaster universal serial bus (USB) port download cable,MasterBlaster TM serial/USB communications cable, ByteBlaster TM IIparallel port download cable, and the ByteBlasterMV TM parallel portdownload cable.In PS configuration with a download cable, an intelligent host (e.g., a PC)transfers data from a storage device to the FPGA via the USB Blaster,MasterBlaster, ByteBlaster II, or ByteBlasterMV cable.Upon power-up, the APEX II device goes through a POR forapproximately 5 μs. During POR, the device resets and holds nSTATUSlow, and tri-states all user I/O pins. Once the FPGA successfully exitsPOR, all user I/O pins are tri-stated. APEX II devices have weak pull-upresistors on the user I/O pins which are on before and duringconfiguration.fThe value of the weak pull-up resistors on the I/O pins that are on beforeand during configuration can be found in the Operating Conditions tableof the APEX II Programmable Logic Device Family Data Sheet.The configuration cycle consists of 3 stages: reset, configuration andinitialization. While nCONFIG or nSTATUS are low, the device is in reset.To initiate configuration in this scheme, the download cable generates alow-to-high transition on the nCONFIG pin.1 VCCINT and VCCIO pins on the banks where the configuration,and JTAG pins reside need to be fully powered to theappropriate voltage levels in order to begin the configurationprocess.When nCONFIG goes high, the device comes out of reset and releases theopen-drain nSTATUS pin, which is then pulled high by an external 1-kΩpull-up resistor. Once nSTATUS is released the FPGA is ready to receiveconfiguration data and the configuration stage begins. The programminghardware or download cable then places the configuration data one bit ata time on the device’s DATA0 pin. The configuration data is clocked intothe target device until CONF_DONE goes high.When using a download cable, setting the Auto-Restart Configuration AfterError option does not affect the configuration cycle because you mustmanually restart configuration in the Quartus II software when an erroroccurs. Additionally, the Enable user-supplied start-up clock (CLKUSR)option has no affect on the device initialization since this option isdisabled in the SOF when programming the FPGA using the Quartus IIprogrammer and download cable. Therefore, if you turn on the CLKUSRAltera Corporation 6–25August 2005 Configuration Handbook, Volume 1