Configuration Handbook - Kamami.pl

JTAG ConfigurationJTAGConfigurationfThe JTAG has developed a specification for boundary-scan testing. Thisboundary-scan test (BST) architecture offers the capability to efficientlytest components on PCBs with tight lead spacing. The BST architecturecan test pin connections without using physical test probes and capturefunctional data while a device is operating normally. You can also use theJTAG circuitry to shift configuration data into the device. The Quartus IIsoftware automatically generates SOFs that can be used for JTAGconfiguration with a download cable in the Quartus II softwareprogrammer.For more information on JTAG boundary-scan testing and commandsavailable using Stratix III devices, refer to the following documents:■■IEEE 1149.1 (JTAG) Boundary-Scan Testing for Stratix III Deviceschapter of the Stratix III Device HandbookJam Programming and Testing Language SpecificationStratix III devices are designed such that JTAG instructions haveprecedence over any device configuration modes. Therefore, JTAGconfiguration can take place without waiting for other configurationmodes to complete. For example, if you attempt JTAG configuration ofStratix III devices during PS configuration, PS configuration is terminatedand JTAG configuration begins.1 You cannot use the Stratix III decompression or design securityfeatures if you are configuring your Stratix III device whenusing JTAG-based configuration.1 A device operating in JTAG mode uses four required pins, TDI,TDO, TMS, and TCK, and one optional pin, TRST. The TCK pin hasan internal weak pull-down resistor, while the TDI, TMS, andTRST pins have weak internal pull-up resistors (typically 25 kΩ).JTAG output pin TDO and all JTAG input pins are powered bythe 2.5 V/3.0 V V CCPD . All the JTAG pins support only LVTTLI/O standard.All user I/O pins are tri-stated during JTAG configuration. Table 11–12explains each JTAG pin's function.11–66 Altera CorporationStratix III Device Handbook, Volume 1 May 2007