Configuration Handbook - Kamami.pl

JTAG ConfigurationOther Altera devices that have JTAG support can be placed in the sameJTAG chain for device programming and configuration.fFor more information about configuring multiple Altera devices in thesame configuration chain, refer to Configuring Mixed Altera FPGA Chainschapter 8 in volume 2 of the Configuration Handbook.The Quartus II software verifies successful JTAG configuration uponcompletion. At the end of configuration, the software checks the state ofCONF_DONE through the JTAG port. If CONF_DONE is not high, theQuartus II software indicates that configuration has failed. If CONF_DONEis high, the software indicates that configuration was successful. WhenQuartus II generates a JAM file for a multi-device chain, it containsinstructions so that all the devices in the chain will be initialized at thesame time.Figure 8–27 shows JTAG configuration of a Mercury, APEX 20K (2.5 V),ACEX 1K, or FLEX 10K FPGA with a microprocessor.Figure 8–27. JTAG Configuration of a Single Device Using a MicroprocessorMemoryADDR DATAMicroprocessorMercury, APEX 20K (2.5-V),ACEX 1K or FLEX 10K DeviceV CCTRSTTDITCKTMSTDO(3) nCEnCEOnCONFIGMSEL0MSEL1nSTATUSCONF_DONEGNDN.C. V CC (1)V CC (1)(2)1 kΩ(2) 1 kΩ(2)Notes to Figure 8–27:(1) The pull-up resistor should be connected to a supply that provides an acceptableinput signal for all devices in the chain.(2) Connect the nCONFIG, MSEL1, and MSEL0 pins to support a non-JTAGconfiguration scheme. If your design only uses JTAG configuration, connect thenCONFIG pin to V CC and the MSEL1 and MSEL0 pins to ground.(3) nCE must be connected to GND or driven low for successful JTAG configuration.Jam STAPLJam STAPL, JEDEC standard JESD-71, is a standard file format for insystemprogrammability (ISP) purposes. Jam STAPL supportsprogramming or configuration of programmable devices and testing ofelectronic systems, using the IEEE 1149.1 JTAG interface. Jam STAPL is afreely licensed open standard.8–62 Altera CorporationConfiguration Handbook, Volume 1 August 2005