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Configuration Handbook - Kamami.pl

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Passive Serial <strong>Configuration</strong>1 To begin configuration, power the V CC , V CCIO , V CCPGM , andV CCPD voltages (for the banks where the configuration and JTAGpins reside) to the appropriate voltage levels.When nCONFIG goes high, the device comes out of reset and releases thenSTATUS pin, which is pulled high by a pull-up resistor. Enhancedconfiguration devices have an optional internal pull-up resistor on the OEpin. This option is available in the Quartus II software from the Generaltab of the Device and Pin Options dialog box. If you do not use thisinternal pull-up resistor, an external 10-kΩ pull-up resistor on theOE-nSTATUS line is required. Once nSTATUS is released, the device isready to receive configuration data and the configuration stage begins.When nSTATUS is pulled high, OE of the configuration device also goeshigh and the configuration device clocks data out serially to the deviceusing the Stratix III device's internal oscillator. The Stratix III devicesreceive configuration data on the DATA0 pin and the clock is received onthe DCLK pin. Data is latched into the device on the rising edge of DCLK.After the device has received all configuration data successfully, itreleases the open-drain CONF_DONE pin, which is pulled high by apull-up resistor. Since CONF_DONE is tied to the configuration device'snCS pin, the configuration device is disabled when CONF_DONE goeshigh. Enhanced configuration devices have an optional internal pull-upresistor on the nCS pin. This option is available in the Quartus II softwarefrom the General tab of the Device and Pin Options dialog box. If thisinternal pull-up resistor is not used, an external 10-kΩ pull-up resistor onthe nCS-CONF_DONE line is required. A low-to-high transition onCONF_DONE indicates configuration is com<strong>pl</strong>ete and initialization of thedevice can begin.In Stratix III devices, the initialization clock source is either the internaloscillator (typically 10 MHz) or the optional CLKUSR pin. By default, theinternal oscillator is the clock source for initialization. If you are using aninternal oscillator, the Stratix III device sup<strong>pl</strong>ies itself with enough clockcycles for proper initialization. You also have the flexibility tosynchronize initialization of multi<strong>pl</strong>e devices or to delay initializationwith the CLKUSR option. You can turn on the Enable user-sup<strong>pl</strong>iedstart-up clock (CLKUSR) option in the Quartus II software from theGeneral tab of the Device and Pin Options dialog box. Sup<strong>pl</strong>ying a clockon CLKUSR will not affect the configuration process. After allconfiguration data has been accepted and CONF_DONE goes high,CLKUSR will be enabled after the time specified as t CD2CU . After this timeperiod elapses, the Stratix III devices require 4,436 clock cycles toinitialize properly and enter user mode. Stratix III devices support aCLKUSR f MAX of 100 MHz.11–52 Altera CorporationStratix III Device <strong>Handbook</strong>, Volume 1 May 2007

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