Configuration Handbook - Kamami.pl

Configuring Stratix III DevicesPS Configuration Using a Download CableIn this section, the generic term "download cable" includes the AlteraUSB-Blaster universal serial bus (USB) port download cable,MasterBlaster serial/USB communications cable, ByteBlaster II parallelport download cable, ByteBlaster MV parallel port download cable,and the EthernetBlaster download cable.In PS configuration with a download cable, an intelligent host (such as aPC) transfers data from a storage device to the device via the USB Blaster,MasterBlaster, ByteBlaster II, EthernetBlaster, or ByteBlasterMV cable.Upon power-up, the Stratix III devices go through a POR. The POR delayis dependent on the PORSEL pin setting. When PORSEL is driven low, thePOR time is approximately 100 ms. If PORSEL is driven high, the PORtime is approximately 12 ms. During POR, the device will reset, holdnSTATUS low, and tri-state all user I/O pins. Once the device successfullyexits POR, all user I/O pins continue to be tri-stated. If nIO_pullup isdriven low during power-up and configuration, the user I/O pins anddual-purpose I/O pins will have weak pull-up resistors which are on(after POR) before and during configuration. If nIO_pullup is drivenhigh, the weak pull-up resistors are disabled.The configuration cycle consists of three stages: reset, configuration andinitialization. While nCONFIG or nSTATUS are low, the device is in reset.To initiate configuration in this scheme, the download cable generates alow-to-high transition on the nCONFIG pin.1 To begin configuration, power the V CC , V CCIO , V CCPGM , andV CCPD voltages (for the banks where the configuration and JTAGpins reside) to the appropriate voltage levels.When nCONFIG goes high, the device comes out of reset and releases theopen-drain nSTATUS pin, which is then pulled high by an external 10-kΩpull-up resistor. Once nSTATUS is released, the device is ready to receiveconfiguration data and the configuration stage begins. The programminghardware or download cable then places the configuration data one bit ata time on the device's DATA0 pin. The configuration data is clocked intothe target device until CONF_DONE goes high. The CONF_DONE pin musthave an external 10-kΩ pull-up resistor in order for the device toinitialize.When using a download cable, setting the Auto-restart configurationafter error option does not affect the configuration cycle because youmust manually restart configuration in the Quartus II software when anerror occurs. Additionally, the Enable user-supplied start-up clock(CLKUSR) option has no affect on the device initialization since thisAltera Corporation 11–61May 2007 Stratix III Device Handbook, Volume 1