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Configuration Handbook - Kamami.pl

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<strong>Configuration</strong> FeaturesV CCPGM PinsStratix III devices offer a new power sup<strong>pl</strong>y, V CCPGM , for all the dedicatedconfiguration pins and dual function pins. <strong>Configuration</strong> voltagesupported is 1.8 V, 2.5 V, and 3.0 V. Stratix III devices do not support 1.5 Vconfiguration.Use this pin to power all dedicated configuration inputs, dedicatedconfiguration outputs, dedicated configuration bidirectional pins, andsome of the dual functional pins that you use for configuration. WithV CCPGM , configuration input buffers do not have to share power lineswith the regular I/O buffer in Stratix III devices.The operating voltage for the configuration input pin is independent ofthe I/O banks power sup<strong>pl</strong>y V CCIO during the configuration. Therefore,no configuration voltage constraints on V CCIO are needed in Stratix IIIdevices.V CCPD PinsStratix III devices have a dedicated programming power sup<strong>pl</strong>y, V CCPD ,which must be connected to 3.0 V /2.5 V in order to power the I/Opre-drivers, the JTAG input and output pins (TCK, TMS, TDI, TDO andTRST), and the design security circuitry.1 V CCPGM and V CCPD must ramp-up from 0 V to the desiredvoltage level within 100 ms. If these sup<strong>pl</strong>ies are not ramped upwithin this specified time, your Stratix III device will notconfigure successfully. If your system does not allow ramp-uptime of 100 ms or less, you must hold nCONFIG low until allpower sup<strong>pl</strong>ies are stable.fFor more information on the configuration pins power sup<strong>pl</strong>y, refer to“Device <strong>Configuration</strong> Pins” on page 11–73.11–10 Altera CorporationStratix III Device <strong>Handbook</strong>, Volume 1 May 2007

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