Configuration Handbook - Kamami.pl

Using Flash Memory to Configure FPGAsThe controller receives a bit of data or a command from the PC ormicroprocessor on the rising and falling edges of the STB signal. Afterreceiving this data, the controller will send an acknowledgement signal tothe PC or microprocessor to initiate sending of the next bit of data. Theacknowledge signal (ACK) should be the same logic level as the lastreceived STB signal. By de-asserting ACK, the controller can stop the PCor microprocessor from sending data. Figure 10–4 shows the STB andACK relationship.Figure 10–4. Sending Acknowledge Signal (ACK) to PC or MicroprocessorSTBData_modeCMD ModeData ModeData (1)ACKNote to Figure 10–4:(1) One bit of data is received at each STB signal edge (both positive and negative).Programming Flash MemoryAfter receiving a command from the PC or microprocessor, the controllerfirst erases and then starts programming the flash memory. A separatestate machine is required to generate a programming command sequenceand programming pulse width.While programming the flash memory, the controller must check if acommand (data_mode=1) has been received or not. A command indicatesthe end of data from the PC or microprocessor, and the controller will exitthe Program_Flash_memory state and go into idle mode.Altera Corporation 10–5April 2007 Configuration Handbook, Volume 2