Configuration Handbook - Kamami.pl

Timing InformationTimingInformationFigure 5–5 shows the timing waveform when using a configurationdevice.Figure 5–5. Timing Waveform Using a Configuration DevicenINIT_CONF or VCC/nCONFIGOE/nSTATUSnCS/CONF_DONEDCLKDATAt PORt CHt DSU t CLt OEZXD0 D1 D2 D3 D n(1)User I/OINIT_DONEt DHt COTri-StateTri-StateUser ModeNote to Figure 5–5:(1) The EPC2 device will drive DCLK low and DATA high after configuration. The EPC1 and EPC1441 device will driveDCLK low and tri-state DATA after configuration.Table 5–8 defines the timing parameters when using EPC2 devices at3.3 V.Table 5–8. Timing Parameters when Using EPC2 devices at 3.3 V (Part 1 of 2)Symbol Parameter Min Typ Max Unitst POR POR delay (1) 200 mst OEZX OE high to DATA output enabled 80 nst CE OE high to first rising edge on DCLK 300 nst DSU Data setup time before rising edge on DCLK 30 nst DH Data hold time after rising edge on DCLK 0 nst CO DCLK to DATA out 30 nst CDOE DCLK to DATA enable/disable 30 nsf CLK DCLK frequency 5 7.7 12.5 MHzt MCH DCLK high time for the first device in the configuration chain 40 65 100 nst MCL DCLK low time for the first device in the configuration chain 40 65 100 nst SCH DCLK high time for subsequent devices 40 nst SCL DCLK low time for subsequent devices 40 nst CASC DCLK rising edge to nCASC 25 ns5–20 Altera CorporationConfiguration Handbook, Volume 2 April 2007