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Configuration Handbook - Kamami.pl

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Configuring APEX II DevicesSince all nSTATUS and CONF_DONE pins are tied together, if any devicedetects an error, configuration stops for the entire chain and the entirechain must be reconfigured. For exam<strong>pl</strong>e, if the first FPGA flags an erroron nSTATUS, it resets the chain by pulling its nSTATUS pin low. Thisbehavior is similar to a single FPGA detecting an error.If the Auto-Restart <strong>Configuration</strong> After Error option is turned on, the FPGAsrelease their nSTATUS pins after a reset time-out period (maximum of 40µs). After all nSTATUS pins are released and pulled high, themicroprocessor can try to reconfigure the chain without needing to pulsenCONFIG low. If this option is turned off, the microprocessor mustgenerate a low-to-high transition (with a low pulse of at least 8 µs) onnCONFIG to restart the configuration process.In your system, you may have multi<strong>pl</strong>e devices that contain the sameconfiguration data. To support this configuration scheme, all device nCEinputs are tied to GND, while nCEO pins are left floating. All otherconfiguration pins (nCONFIG, nSTATUS, DCLK, DATA[7..0], andCONF_DONE) are connected to every device in the chain. You should payspecial attention to the configuration signals because they may requirebuffering to ensure signal integrity and prevent clock skew problems.Specifically, ensure that the DCLK and DATA lines are buffered for everyfourth device. Devices must be the same density and package. All deviceswill start and com<strong>pl</strong>ete configuration at the same time. Figure 6–22 showsmulti-device FPP configuration when both APEX II devices are receivingthe same configuration data.Altera Corporation 6–43August 2005 <strong>Configuration</strong> <strong>Handbook</strong>, Volume 1

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