Configuration Handbook - Kamami.pl

Device Configuration Overviewrelated I/O banks (3, 4, 7, and 8) where the following pins reside: TDI,TMS, TCK, TRST, MSEL0, MSEL1, MSEL2, nCONFIG, nCE, DCLK, PLL_ENA,CONF_DONE, nSTATUS. The VCCSEL pin can be pulled to 1.5, 1.8, 2.5, or3.3-V for a logic high level. There is an internal 2.5-kΩ pull-down resistoron VCCSEL. Therefore, if you are using a pull-up resister to pull up thissignal, you need to use a 1-kΩ resistor.VCCSEL also sets the power-on-reset (POR) trip point for all theconfiguration related I/O banks (3, 4, 7, and 8), ensuring that these I/Obanks have powered up to the appropriate voltage levels beforeconfiguration begins. Upon power-up, the FPGA does not releasenSTATUS until V CCINT and all of the V CCIO s of the configuration I/Obanks are above their POR trip points. If you set VCCSEL to ground (logiclow), this sets the POR trip point for all configuration I/O banks to avoltage consistent with 3.3-V/2.5-V signaling. When VCCSEL = 0, thePOR trip point for these I/O banks may be as high as 1.8 V. If V CCIO of anyof the configuration banks is set to 1.8 or 1.5 V, the voltage supplied to thisI/O bank(s) may never reach the POR trip point, which will not allow theFPGA to begin configuration.1 If the V CCIO of I/O banks 3, 4, 7, or 8 is set to 1.5 or 1.8 V and theconfiguration signals used require 3.3-V or 2.5-V signaling youshould set VCCSEL to V CC (logic high) in order to lower the PORtrip point to enable successful configuration.Table 11–3 shows how you should set the VCCSEL depending on theV CCIO setting of the configuration I/O banks and your configurationinput signaling voltages.Table 11–3. VCCSEL SettingV CCIO (banks 3,4,7,8)Configuration InputSignaling VoltageV CCSEL3.3-V/2.5-V 3.3-V/2.5-V GND1.8-V/1.5-V 3.3-V/2.5-V/1.8-V/1.5-V VCC3.3-V/2.5-V 1.8-V/1.5-V Not SupportedThe VCCSEL signal does not control any of the dual-purpose pins,including the dual-purpose configuration pins, such as the DATA[7..0]and PPA pins (nWS, nRS, CS, nCS, and RDYnBSY). During configuration,these dual-purpose pins drive out voltage levels corresponding to theV CCIO supply voltage that powers the I/O bank containing the pin. Afterconfiguration, the dual-purpose pins inherit the I/O standards specifiedin the design.11–4 Altera CorporationStratix Device Handbook, Volume 2 July 2005