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Configuration Handbook - Kamami.pl

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Clock DividerFigure 3–12. Selecting Compression ModeCalculating the Size of <strong>Configuration</strong> SpaceWhen using 1-bit PS configuration mode to serially configure multi<strong>pl</strong>edevices, all configuration data is transmitted through the same DATA lineand the devices are daisy-chained together. Therefore, the total size of theuncompressed configuration data is equal to the sum of the SRAM-baseddevice’s configuration file size multi<strong>pl</strong>ied by the number of pages used.When using n-bit PS configuration mode to concurrently configuremulti<strong>pl</strong>e devices, each SRAM-based device has its own DATA line fromthe enhanced configuration devices. The total size of the uncompressedconfiguration space is equal to the size of the largest device’sconfiguration file size multi<strong>pl</strong>ied by n (where n = 1, 2, 4, or 8), which isthen multi<strong>pl</strong>ied by the number of pages used. For exam<strong>pl</strong>e, if threedevices are concurrently configured using 4-bit PS configuration mode,the total size of the uncompressed configuration space is equal to the sizeof the largest device’s configuration file multi<strong>pl</strong>ied by four.When using FPP configuration mode, the total size of the uncompressedconfiguration space is equal to the sum of the SRAM-based device’sconfiguration file size multi<strong>pl</strong>ied by the number of pages used.For configuration file sizes of SRAM-based devices, refer to the<strong>Configuration</strong> <strong>Handbook</strong>.Clock DividerThe clock divider value specifies the clock frequency divisor, which isused to determine the DCLK frequency, or how fast the data is clocked intothe SRAM-based device. You must consider the maximum DCLK input3–18 Altera Corporation<strong>Configuration</strong> <strong>Handbook</strong>, Volume 2 April 2007

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