Configuration Handbook - Kamami.pl

Configuring Stratix II & Stratix II GX DevicesTable 7–21. Stratix II Configuration Pin Summary (Part 2 of 2) Note (1)Bank Description Input/Output Dedicated Powered By Configuration Mode7 PLL_ENA Input Yes (3) Optional7 nCEO Output Yes (2), (4) All modes4 MSEL[3..0] Input Yes VCCINT All modes4 TDO Output Yes (2), (4) JTAGNotes to Table 7–21:(1) Total number of pins is 41, total number of dedicated pins is 19.(2) All outputs are powered by VCCIO except as noted.(3) All inputs are powered by VCCIO or VCCPD, based on the VCCSEL setting, except as noted.(4) An external pull-up resistor may be required for this configuration pin because of the multivolt I/O interface. Referto the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook for pull-up or level shifterrecommendations for nCEO and TDO.Figure 7–38 shows the I/O bank locations.Figure 7–38. Stratix II I/O Bank NumbersBank 3 Bank 4Bank 1Bank 6Bank 2Bank 5Stratix II DeviceI/O Bank NumbersBank 8 Bank 7Altera Corporation 7–93May 2007 Stratix II Device Handbook, Volume 2