Configuration Handbook - Kamami.pl

Passive Parallel Asynchronous ConfigurationFigure 7–30. Single Device PPA Configuration Using a MicroprocessorAddress DecoderADDRV CC(2)MemoryADDR DATA[7..0]10 kΩV CC(2)10 kΩStratix II or Stratix II GXDeviceMicroprocessorGNDnCS (1)CS (1)CONF_DONEnSTATUSnCEDATA[7..0]nWSnRSnCONFIGRDYnBSYMSEL3MSEL2MSEL1MSEL0nCEODCLKN.C.(2)V CC10 kΩV CCGNDNotes to Figure 7–30:(1) If not used, the CS pin can be connected to V CC directly. If not used, the nCS pin can be connected to GND directly.(2) The pull-up resistor should be connected to a supply that provides an acceptable input signal for the device. V CCshould be high enough to meet the V IH specification of the I/O on the device and the external host.During PPA configuration, it is only required to use either the nCS or CSpin. Therefore, if you are using only one chip-select input, the other mustbe tied to the active state. For example, nCS can be tied to ground whileCS is toggled to control configuration. The device’s nCS or CS pins can betoggled during PPA configuration if the design meets the specificationsset for t CSSU , t WSP , and t CSH listed in Table 7–18.Upon power-up, the Stratix II and Stratix II GX devices go through aPOR. The POR delay is dependent on the PORSEL pin setting. WhenPORSEL is driven low, the POR time is approximately 100 ms. If PORSELis driven high, the POR time is approximately 12 ms. During POR, thedevice will reset, hold nSTATUS low, and tri-state all user I/O pins. Oncethe device successfully exits POR, all user I/O pins continue to betri-stated. If nIO_pullup is driven low during power-up andconfiguration, the user I/O pins and dual-purpose I/O pins will haveweak pull-up resistors which are on (after POR) before and duringconfiguration. If nIO_pullup is driven high, the weak pull-up resistorsare disabled.7–74 Altera CorporationStratix II Device Handbook, Volume 2 May 2007