Configuration Handbook - Kamami.pl

Configuration Schemesattempt JTAG configuration in Cyclone FPGAs during non-JTAGconfiguration, non-JTAG configuration is terminated and JTAGconfiguration is initiated.1 The Cyclone configuration data decompression feature is notsupported in JTAG-based configuration.A device operating in JTAG mode uses four required pins: TDI, TDO, TMS,and TCK. Cyclone FPGAs do not support the optional TRST pin. The threeJTAG input pins, TCK, TDI, and TMS, have weak internal pull-upresistors, whose values are approximately 20 to 40 kΩ. All user I/O pinsare tri-stated during JTAG configuration.Table 13–6 shows each JTAG pin’s function.Table 13–6. JTAG Pin DescriptionsPin Description FunctionTDI Test data input Serial input pin for instructions as well as test and programming data. Data isshifted in on the rising edge of TCK. If the JTAG interface is not required on theboard, the JTAG circuitry can be disabled by connecting this pin to V CC .TDO Test data output Serial data output pin for instructions as well as test and programming data. Datais shifted out on the falling edge of TCK. The pin is tri-stated if data is not beingshifted out of the device. If the JTAG interface is not required on the board, theJTAG circuitry can be disabled by leaving this pin unconnected.TMS Test mode select Input pin that provides the control signal to determine the transitions of the TestAccess Port (TAP) controller state machine. Transitions within the state machineoccur on the rising edge of TCK. Therefore, TMS must be set up before the risingedge of TCK. TMS is evaluated on the rising edge of TCK. If the JTAG interfaceis not required on the board, the JTAG circuitry can be disabled by connectingthis pin to V CC .TCK Test clock input The clock input to the BST circuitry. Some operations occur at the rising edge,while others occur at the falling edge. If the JTAG interface is not required on theboard, the JTAG circuitry can be disabled, by connecting this pin to GND.JTAG Configuration Using a Download CableDuring JTAG configuration, data is downloaded to the device on theboard through a USB Blaster, ByteBlaster II, ByteBlasterMV, orMasterBlaster download cable. Configuring devices through a cable issimilar to programming devices in-system. See Figure 13–19 for pinconnection information.13–32 Altera CorporationCyclone Device Handbook, Volume 1 January 2007