Configuration Handbook - Kamami.pl

Configuring Cyclone FPGAsFigure 13–5. AS Configuration of a Single Cyclone FPGAV CC (1) V CC (1) V CC (1)10 kΩ10 kΩ10 kΩSerial ConfigurationDeviceCyclone FPGAnSTATUSCONF_DONE nCEOnCONFIGnCEN.C.DATAGNDDATA0DCLKDCLKnCSnCSOMSEL1ASDI(2)ASDOMSEL0Notes to Figure 13–5:(1) Connect the pull-up resistors to a 3.3-V supply.(2) Cyclone FPGAs use the ASDO to ASDI path to control the configuration device.GNDConnecting the MSEL[1..0] pins to 00 selects the AS configurationscheme. The Cyclone chip enable signal, nCE, must also be connected toground or driven low for successful configuration.During system power up, both the Cyclone FPGA and serialconfiguration device enter a power-on reset (POR) period. As soon as theCyclone FPGA enters POR, it drives nSTATUS low to indicate it is busyand drives CONF_DONE low to indicate that it has not been configured.After POR, which typically lasts 100 ms, the Cyclone FPGA releasesnSTATUS and enters configuration mode when this signal is pulled highby the external 10-kΩ resistor. Once the FPGA successfully exits POR, alluser I/O pins are tri-stated. Cyclone devices have weak pull-up resistorson the user I/O pins which are on before and during configuration.fThe value of the weak pull-up resistors on the I/O pins that are onbefore and during configuration can be found in Chapter 4, DC &Switching Characteristics.The serial clock (DCLK) generated by the Cyclone FPGA controls theentire configuration cycle (see Figure 13–1 on page 13–2) and this clocksignal provides the timing for the serial interface. Cyclone FPGAs use anAltera Corporation 13–9January 2007 Cyclone Device Handbook, Volume 1