Configuration Handbook - Kamami.pl

Configuring Stratix & Stratix GX DevicesThe Quartus II software verifies successful JTAG configuration uponcompletion. The software checks the state of CONF_DONE through theJTAG port. If CONF_DONE is not in the correct state, the Quartus IIsoftware indicates that configuration has failed. If CONF_DONE is in thecorrect state, the software indicates that configuration was successful.1 If VCCIO is tied to 3.3 V, both the I/O pins and JTAG TDO portdrive at 3.3-V levels.Do not attempt JTAG and non-JTAG configuration simultaneously. Whenconfiguring through JTAG, allow any non-JTAG configuration tocomplete first.Figure 11–22 shows the JTAG configuration of a Stratix or Stratix GXdevice with a microprocessor.Figure 11–22. JTAG Configuration of Stratix & Stratix GX Devices with aMicroprocessorMemoryStratix orStratix GX DeviceADDR DATAMicroprocessor(1)(2)(2)nCONFIGDATA0DCLKTDITCKTMSMSEL2MSEL1MSEL0TDOnSTATUSCONF_DONE(1)(1)(1)V CC10 kΩV CC10 kΩNotes to Figure 11–22:(1) Connect the nCONFIG, MSEL2, MSEL1, and MSEL0 pins to support a non-JTAGconfiguration scheme. If your design only uses JTAG configuration, connect thenCONFIG pin to V CC and the MSEL2, MSEL1, and MSEL0 pins to ground.(2) Pull DATA0 and DCLK to either high or low.Configuration with JRunner Software DriverJRunner is a software driver that allows you to configure Altera FPGAsthrough the ByteBlasterMV download cable in JTAG mode. Theprogramming input file supported is in Raw Binary File (.rbf) format.JRunner also requires a Chain Description File (.cdf) generated by theQuartus II software. JRunner is targeted for embedded JTAGconfiguration. The source code has been developed for the Windows NToperating system. You can customize the code to make it run on otherplatforms.Altera Corporation 11–41July 2005 Stratix Device Handbook, Volume 2