Configuration Handbook - Kamami.pl

Configuring APEX 20KE & APEX 20KC DevicesFigure 7–9. Single Device PS Configuration Using a MicroprocessorMemoryADDRDATA0(1) VCC VCC (1)10 kΩ 10 kΩAPEX 20KE orAPEX 20KC DeviceMicroprocessorGNDCONF_DONEnSTATUSnCEMSEL1MSEL0nCEOGNDN.C.DATA0nCONFIGDCLKNote to Figure 7–9:(1) Connect the pull-up resistor to a supply that provides an acceptable input signalfor the device.Upon power-up, the APEX 20KE or APEX 20KC device goes through aPOR for approximately 5 µs. During POR, the device resets and holdsnSTATUS low, and tri-states all user I/O pins. Once the FPGAsuccessfully exits POR, all user I/O pins are tri-stated. APEX 20KE andAPEX 20KC devices have weak pull-up resistors on the user I/O pinswhich are on before and during configuration.fThe value of the weak pull-up resistors on the I/O pins that are on beforeand during configuration can be found in the Operating Conditions tableof the APEX 20K Programmable Logic Device Family Data Sheet orAPEX 20KC Programmable Logic Device Family Data Sheet.The configuration cycle consists of three stages: reset, configuration, andinitialization. While nCONFIG or nSTATUS are low, the device is in reset.To initiate configuration, the microprocessor must generate a low-to-hightransition on the nCONFIG pin.1 VCCINT and VCCIO pins on the banks where the configurationand JTAG pins reside need to be fully powered to theappropriate voltage levels in order to begin the configurationprocess.When nCONFIG goes high, the device comes out of reset and releases theopen-drain nSTATUS pin, which is then pulled high by an external 10-kΩpull-up resistor. Once nSTATUS is released, the FPGA is ready to receiveconfiguration data and the configuration stage begins. When nSTATUS isAltera Corporation 7–21August 2005 Configuration Handbook, Volume 1