Configuration Handbook - Kamami.pl

Device Configuration PinsTable 13–10. Dedicated Cyclone Device Configuration Pins (Part 3 of 3)Pin NameDCLK – PSASASDOnCSOUserModeI/O in PSmode,N/A in ASmodeI/O in PSmode,N/A in ASmodeConfigurationSchemePin TypeInput (PS)Output (AS)DescriptionIn PS configuration, the clock input clocks data froman external source into the target device. Data islatched into the FPGA on the rising edge of DCLK. InAS configuration, DCLK is an output from the CycloneFPGA that provides timing for the configurationinterface. After configuration, the logic levels on thispin do not affect the Cyclone FPGA. This pin usesSchmitt trigger input buffersAS Output Control signal from the Cyclone FPGA to the serialconfiguration device in AS mode used to read outconfiguration data.AS Output Output control signal from the Cyclone FPGA to theserial configuration device in AS mode that enablesthe configuration device.nCE – All Input Active-low chip enable. The nCE pin activates thedevice with a low signal to allow configuration. ThenCE pin must be held low during configuration,initialization, and user mode. In single deviceconfiguration, tie the nCE pin low. In multi-deviceconfiguration, the first device’s nCE pin is tied lowwhile its nCEO pin is connected to nCE of the nextdevice in the chain. Hold the nCE pin low forprogramming the FPGA via JTAG. This pin usesSchmitt trigger input buffersnCEO – All Output Output that drives low when device configuration iscomplete. In single device configuration, this pin is leftfloating. In multi-device configuration, this pin feedsthe next device's nCE pin. The nCEO of the lastdevice in the chain is left floating.DATA0 – All Input Data input. In serial configuration mode, bit-wideconfiguration data is presented to the target device onthe DATA0 pin. Toggling DATA0 after configurationdoes not affect the configured device. This pin usesSchmitt trigger input buffers13–48 Altera CorporationCyclone Device Handbook, Volume 1 January 2007