Configuration Handbook - Kamami.pl

Configuring APEX II DevicesFigure 6–10. Multi-Device PS Configuration Using a MicroprocessorMemoryADDRDATA0VCC (1)VCC (1)1 kΩ 1 kΩAPEX II Device 1APEX II Device 2CONF_DONEMSEL1MSEL0CONF_DONEMSEL1MSEL0MicroprocessorGNDnSTATUSnCEDATA0nCONFIGnCEOGNDnSTATUSnCEDATA0nCONFIGnCEOGNDN.C.DCLKDCLKNote to Figure 6–10:(1) The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in thechain.In multi-device PS configuration the first device’s nCE pin is connected toGND while its nCEO pin is connected to nCE of the next device in thechain. The last device’s nCE input comes from the previous device, whileits nCEO pin is left floating. After the first device completes configurationin a multi-device configuration chain, its nCEO pin drives low to activatethe second device’s nCE pin, which prompts the second device to beginconfiguration. The second device in the chain begins configuration withinone clock cycle; therefore, the transfer of data destinations is transparentto the microprocessor. All other configuration pins (nCONFIG, nSTATUS,DCLK, DATA0, and CONF_DONE) are connected to every device in thechain. You should pay special attention to the configuration signalsbecause they can require buffering to ensure signal integrity and preventclock skew problems. Specifically, ensure that the DCLK and DATA linesare buffered for every fourth device. Because all device CONF_DONE pinsare tied together, all devices initialize and enter user mode at the sametime.Since all nSTATUS and CONF_DONE pins are tied together, if any devicedetects an error, configuration stops for the entire chain and the entirechain must be reconfigured. For example, if the first FPGA flags an erroron nSTATUS, it resets the chain by pulling its nSTATUS pin low. Thisbehavior is similar to a single FPGA detecting an error.Altera Corporation 6–21August 2005 Configuration Handbook, Volume 1